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"Variation-Conscious Formal Timing Verification in RTL."

Jayanand Asok Kumar, Shobha Vasudevan (2011)

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DOI: 10.1109/VLSID.2011.48

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Jayanand Asok Kumar, Shobha Vasudevan:
Variation-Conscious Formal Timing Verification in RTL. VLSI Design 2011: 58-63

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