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Narumi Sakashita
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1990 – 1999
- 1999
- [j5]Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura:
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. IEEE J. Solid State Circuits 34(8): 1084-1090 (1999) - 1997
- [j4]Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma:
A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. IEEE J. Solid State Circuits 32(11): 1712-1720 (1997) - [c4]T. Iwamoto, S. Kobashi, Narumi Sakashita, J. Mitsuishi, Ken-ichi Tanaka, Kazuo Kyuma:
Reduction of the Test Time for Mass Produced LSI Devices by Genetic Algorithms. ICONIP (1) 1997: 704-707 - 1996
- [j3]Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe:
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. IEEE J. Solid State Circuits 31(11): 1645-1655 (1996) - [c3]Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe:
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. ITC 1996: 319-324 - 1993
- [j2]Kazuo Nakamura, Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Takeshi Tokuda:
Fuzzy inference and fuzzy inference processor. IEEE Micro 13(5): 37-48 (1993) - [c2]Eiichi Teraoka, Toru Kengaku, Ikuo Yasui, Kazuyuki Ishikawa, Takahiro Matsuo, Hideyuki Wakada, Narumi Sakashita, Yukihiko Shimazu, Takeshi Tokuda:
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC. ITC 1993: 791-796 - 1990
- [c1]Narumi Sakashita, Hisako Sawai, Eiichi Teraoka, Toshiki Fugiyama, Toru Kengaku, Yukihiko Shimazu, Takeshi Tokuda:
Built-in self-test in a 24 bit floating point digital signal processor. ITC 1990: 880-885
1980 – 1989
- 1988
- [j1]Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa:
A macrocell approach for VLSI processor design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12): 1272-1277 (1988)
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