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João Navarro Jr.
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2010 – 2019
- 2013
- [c14]Eder Issao Ishibe, Joao Navarro Soares:
A CMOS bandgap reference circuit with a temperature coefficient adjustment block. SBCCI 2013: 1-6 - 2011
- [c13]Joao Navarro Soares
, Eder Ishibe:
A simple CMOS bandgap reference circuit with sub-1-V operation. ISCAS 2011: 2289-2292 - [c12]João Navarro Jr.
Design of high speed digital circuits with E-TSPC cell library. SBCCI 2011: 167-172
2000 – 2009
- 2007
- [c11]Fernando P. H. de Miranda, João Navarro Jr.
A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures. ISCAS 2007: 1895-1898 - [c10]Hugo Daniel Hernández
A small area 8bits 50MHz CMOS DAC for bluetooth transmitter. SBCCI 2007: 10-15 - [c9]Fernando P. H. de Miranda, João Navarro Jr.
A 4.1 GHz prescaler using double data throughput E-TSPC structures. SBCCI 2007: 123-127 - 2006
- [c8]Alexandre J. Aragão
Mismatch effect analyses in CMOS tapered buffers. ISCAS 2006 - 2005
- [c7]Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije:
A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. SBCCI 2005: 144-148 - 2004
- [c6]Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije:
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology. SBCCI 2004: 94-99 - 2003
- [c5]Elkim Roa, Joao Navarro Soares, Wilhelmus A. M. Van Noije:
A Methodology for CMOS Low Noise Ampli.er Design. SBCCI 2003: 14-19 - 2002
- [j3]João Navarro Jr.
Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 301-308 (2002) - 2000
- [c4]Joao Navarro Soares, Wilhelmus A. M. Van Noije:
The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data Throughput. SBCCI 2000: 228-236
1990 – 1999
- 1999
- [j2]Joao Navarro Soares, Wilhelmus A. M. Van Noije:
A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC). IEEE J. Solid State Circuits 34(1): 97-102 (1999) - 1998
- [c3]João Navarro Jr., Wilhelmus A. M. Van Noije:
CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation. Great Lakes Symposium on VLSI 1998: 89-94 - [c2]João Navarro Jr., Wilhelmus A. M. Van Noije:
Design of an 8: 1 MUX at 1.7Gbit/s in 0.8µm CMOS Technology. Great Lakes Symposium on VLSI 1998: 103-107 - 1997
- [c1]João Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije:
A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems. Great Lakes Symposium on VLSI 1997: 14- - 1995
- [j1]Wilhelmus A. M. Van Noije, W. T. Liu, João Navarro Jr.
Precise final state determination of mismatched CMOS latches. IEEE J. Solid State Circuits 30(5): 607-611 (1995)
Coauthor Index
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