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SBCCI 2013: Curitiba, Brazil
- 26th Symposium on Integrated Circuits and Systems Design, SBCCI 2013, Curitiba, Brazil, September 2-6, 2013. IEEE 2013
- Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian
, Renato P. Ribas, André Inácio Reis:
Spin diode network synthesis using functional composition. 1-6 - Christoph Roth, Harald Bucher, Simon Reder, Florian Buciuman, Oliver Sander, Jürgen Becker
A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation. 1-6 - Cicero Nunes, Paulo F. Butzen
A methodology to evaluate the aging impact on flip-flops performance. 1-6 - Julian J. H. Pontes, Ney Calazans
H2A: A hardened asynchronous network on chip. 1-6 - Wanderson Roger Azevedo Dias
A new code compression algorithm and its decompressor in FPGA-based hardware. 1-6 - Gustavo Campos Martins, Fernando Rangel de Sousa
An RF-powered temperature sensor designed for biomedical applications. 1-6 - Eduardo A. C. da Costa
Gray encoded fixed-point LMS adaptive filter architecture for the harmonics power line interference cancelling. 1-6 - Tiago Oliveira Weber
Synthesis of a narrow-band Low Noise Amplifier in a 180 nm CMOS technology using Simulated Annealing with crossover operator. 1-5 - Lucas C. Severo
A methodology for the automatic design of operational amplifiers including yield optimization. 1-6 - SungHa Jung, Myoung-Seob Lim, Yihu Xu, Dae Hyun Jo:
Implementation of split-radix FFT pruning for the reduction of computational complexity in OFDM based cognitive radio system. 1-5 - Kleber Stangherlin, Sergio Bampi
Energy-speed exploration for very-wide range of dynamic V-F scaling. 1-6 - André Luiz Aita, Cesar Ramos Rodrigues
PTAT CMOS current sources mismatch over temperature. 1-4 - Fernando de Souza Campos
Temporal noise analysis and measurements of CMOS active pixel sensor operating in time domain. 1-5 - Johanna Sepúlveda, Guy Gogniat
Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection. 1-6 - Leandro Zafalon Pieper, Eduardo A. C. da Costa
Combination of radix-2m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers. 1-6 - Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Read-polarity-once Boolean functions. 1-6 - Fernando Paixão Cortes, Guilherme Freitas, Henrique Luiz Andrade Pimentel, Juan Pablo Martinez Brito, Fernando Chávez:
Low-Power/Low-Voltage analog front-end for LF passive RFID tag systems. 1-6 - Hamilton Klimach, Arthur Liraneto Torres Costa, Moacir Fernandes Cortinhas Monteiro, Sergio Bampi
A resistorless switched bandgap voltage reference with offset cancellation. 1-5 - Joachim Meyer, Michael Dreschmann, Djorn Karnick, Philipp C. Schindler, Wolfgang Freude
A novel system on chip for software-defined, high-speed OFDM signal processing. 1-6 - Alberto Wiltgen, Kim A. Escobar, André Inácio Reis, Renato P. Ribas:
Power consumption analysis in static CMOS gates. 1-6 - Johanna Sepúlveda, Guy Gogniat
An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs. 1-6 - Leandro Nunes, Ricardo Reis
Global routing congestion reduction with cost allocation look-ahead. 1-5 - Karolinne Brito, Fernando Rangel de Sousa
A 400 MHz reconfigurable injection-locking based RC oscillator for ASK/FSK modulation. 1-4 - Caio G. P. Alegretti, Vinícius Dal Bem, Renato P. Ribas, André Inácio Reis:
Analytical logical effort formulation for minimum active area under delay constraints. 1-6 - Abner Luis Panho Marciano, Andre B. Oliveira, José Augusto Miranda Nacif, Omar P. Vilela Neto
An efficient FPGA implementation in quantum-dot cellular automata. 1-6 - Edson Sorato, Eduardo P. Fronza, Paulo R. F. M. M. Barbosa, José Luís Almada Güntzel, Adalbery R. Castro, Aldebaro Klautau
Real-time digital modulation classification based on Support Vector Machines. 1-6 - Eder Issao Ishibe, Joao Navarro Soares:
A CMOS bandgap reference circuit with a temperature coefficient adjustment block. 1-6 - Iuri A. C. Gomes, Fernanda Gusmão de Lima Kastensmidt
Reducing TMR overhead by combining approximate circuit, transistor topology and input permutation approaches. 1-6 - Guilherme H. K. Martini, João Alberto Fabro
Hybrid filter for high-power converter systems. 1-6 - Tony Forzley, Ralph Mason:
A 14b threshold configurable dynamically latched comparator for SAR ADCs. 1-5 - Kim A. Escobar, Renato P. Ribas:
Parallel prefix adder design using quantum-dot cellular automata. 1-6 - Yan Ghidini, Matheus T. Moreira, Lucas Brahm, Thais Webber
Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy. 1-6 - Juan Pablo Martinez Brito, Alain Rabaeijs:
CMOS smart temperature sensors for RFID applications. 1-6 - Jose Luis Garcia-Gervacio, Agustín Leobardo Herrera-May
Voltage Regulation System for UHF RFID Tags. 1-6 - Ismael Seidel, Bruno George de Moraes, André Beims Bräscher, José Luís Güntzel:
On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation. 1-6 - Ruhan A. Conceição
Hardware design for the 32×32 IDCT of the HEVC video coding standard. 1-6 - Pedro F. G. da Silva, Eduardo G. Lima
Design of crest factor reduction techniques based on clipping and filtering for wireless communications systems. 1-5 - Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Improving the methodology to build non-series-parallel transistor arrangements. 1-6 - Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Synthesis of threshold logic gates to nanoelectronics. 1-6 - Fabricio G. S. Silva, Robson Nunes de Lima
A 433/915-MHz class AB discrete power amplifier based on multiresonant circuits. 1-6 - Jan Heisswolf, Simon Bischof, Michael Rückauer, Jürgen Becker
Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers. 1-6 - Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Delay model for static CMOS complex gates. 1-6
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