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Shuhei Tanakamaru
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2010 – 2019
- 2016
- [j13]Hirofumi Takishita, Shuhei Tanakamaru, Sheyang Ning, Ken Takeuchi:
Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths. IEICE Trans. Electron. 99-C(4): 444-451 (2016) - [j12]Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes, Ken Takeuchi:
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. IEEE J. Solid State Circuits 51(8): 1938-1951 (2016) - [j11]Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi, Hirofumi Takishita, Ken Takeuchi:
Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2208-2219 (2016) - 2015
- [j10]Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi:
A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories. IEICE Trans. Electron. 98-C(1): 53-61 (2015) - [j9]Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi:
Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs). IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 771-780 (2015) - [j8]Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi:
Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 844-853 (2015) - [c10]Tsukasa Tokutomi, Masafumi Doi, Shogo Hachiya, Atsuro Kobayashi, Shuhei Tanakamaru, Ken Takeuchi:
7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage. ISSCC 2015: 1-3 - [c9]Senju Yamazaki, Shuhei Tanakamaru, Sakuya Suzuki, Tomoko Ogura Iwasaki, Shogo Hachiya, Ken Takeuchi:
Reliability enhancement of 1Xnm TLC for cold flash and millennium memories. VLSIC 2015: 112- - [c8]Shuhei Tanakamaru, Hiroki Yamazawa, Ken Takeuchi:
Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten. VLSIC 2015: 130- - 2014
- [j7]Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi:
NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1119-1132 (2014) - [c7]Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi:
19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers. ISSCC 2014: 336-337 - [c6]Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi:
Application-aware solid-state drives (SSDs) with adaptive coding. VLSIC 2014: 1-2 - 2013
- [j6]Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi:
Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs). IEEE J. Solid State Circuits 48(11): 2920-2933 (2013) - [c5]Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi:
Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme. ASP-DAC 2013: 83-84 - [c4]Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi:
Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications. ISSCC 2013: 226-227 - 2012
- [j5]Ken Takeuchi, Teruyoshi Hatanaka, Shuhei Tanakamaru:
Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs). IEICE Electron. Express 9(8): 779-794 (2012) - [j4]Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi:
Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor. IEICE Trans. Electron. 95-C(4): 564-571 (2012) - [j3]Shuhei Tanakamaru, Chinglin Hung, Ken Takeuchi:
Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming. IEEE J. Solid State Circuits 47(1): 85-96 (2012) - [c3]Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi:
Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme. ISSCC 2012: 424-426 - 2011
- [j2]Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano, Ken Takeuchi:
Improvement of Read Margin and Its Distribution by VTH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection. IEEE J. Solid State Circuits 46(9): 2180-2188 (2011) - [j1]Shuhei Tanakamaru, Ken Takeuchi:
A 0.5 V Operation V TH Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems. IEEE J. Solid State Circuits 46(10): 2406-2415 (2011) - [c2]Shuhei Tanakamaru, Chinglin Hung, Atsushi Esumi, Mitsuyoshi Ito, Kai Li, Ken Takeuchi:
95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm. ISSCC 2011: 204-206 - 2010
- [c1]Kentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi:
Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor. CICC 2010: 1-4
Coauthor Index
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