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Federico Nicolás Peccia
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2020 – today
- 2024
- [c6]Federico Nicolás Peccia, Alexander Viehl, Oliver Bringmann:
DIAPASON: Differentiable Allocation, Partitioning and Fusion of Neural Networks for Distributed Inference. DATE 2024: 1-6 - [c5]Federico Nicolás Peccia, Svetlana Pavlitska, Tobias Fleck, Oliver Bringmann:
Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator. DSD 2024: 418-426 - [c4]Svetlana Pavlitska, Oliver Bagge, Federico Nicolás Peccia, Toghrul Mammadov, J. Marius Zöllner:
Iterative Filter Pruning for Concatenation-based CNN Architectures. IJCNN 2024: 1-10 - [i5]Federico Nicolás Peccia
, Oliver Bringmann:
Embedded Distributed Inference of Deep Neural Networks: A Systematic Review. CoRR abs/2405.03360 (2024) - [i4]Svetlana Pavlitska, Oliver Bagge, Federico Nicolás Peccia
Iterative Filter Pruning for Concatenation-based CNN Architectures. CoRR abs/2405.03715 (2024) - [i3]Federico Nicolás Peccia, Svetlana Pavlitska, Tobias Fleck, Oliver Bringmann:
Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator. CoRR abs/2408.07404 (2024) - [i2]Konstantin Lübeck, Alexander Louis-Ferdinand Jung, Felix Wedlich, Mika Markus Müller, Federico Nicolás Peccia, Felix Thömmes, Jannik Steinmetz, Valentin Biermaier, Adrian Frischknecht, Paul Palomero Bernardo, Oliver Bringmann:
Automatic Generation of Fast and Accurate Performance Models for Deep Neural Network Accelerators. CoRR abs/2409.08595 (2024) - 2023
- [c3]Federico Nicolás Peccia
Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning framework. CODAI 2023: 21-26 - [c2]Maximilian Kirschner, Federico Nicolás Peccia
Characterization of Execution Time Variability in FPGA-Based AI-Accelerators. DASC/PiCom/CBDCom/CyberSciTech 2023: 1-8 - [c1]Tobias Fleck, Svetlana Pavlitska, Sven Nitzsche, Brian Pachideh, Federico Nicolás Peccia
Low-Power Traffic Surveillance using Multiple RGB and Event Cameras: A Survey. ISC2 2023: 1-7 - 2022
- [i1]Federico Nicolás Peccia
Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning framework. CoRR abs/2212.03034 (2022)
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