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Dengquan Li
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- affiliation: Xidian University, Xian, Shaanxi, China
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2020 – today
- 2024
- [j28]Jiale Ding, Yukai Huang, Hao Zhang, Tian Feng, Feida Wang, Dengquan Li
, Zhangming Zhu:
A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture. Microelectron. J. 144: 106095 (2024) - [j27]Longsheng Wang
FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 3975-3985 (2024) - [j26]Hongzhi Liang
A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 81-85 (2024) - [j25]Dengquan Li
A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm. IEEE Trans. Instrum. Meas. 73: 1-10 (2024) - [j24]Longsheng Wang
LUT-Assisted Particle Swarm Optimization-Based Bit-Weight Calibration for SAR ADCs. IEEE Trans. Instrum. Meas. 73: 1-11 (2024) - [j23]Dengquan Li
A Wideband Input Buffer Based on Cascade Complementary Source Follower. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 962-966 (2024) - [c6]Dengquan Li, Yexin Zhu, Longsheng Wang, Shubin Liu, Zhangming Zhu:
Low-Cost Linearity Testing of High-Resolution ADCs Using Segmentation Modeling and Partial Polynomial Fitting. ISCAS 2024: 1-4 - 2023
- [j22]Dengquan Li
A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3557-3566 (2023) - [j21]Yi Shen
An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1870-1873 (2023) - [j20]Xin Zhao
An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2147-2151 (2023) - [c5]Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong
A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage. CICC 2023: 1-2 - 2022
- [j19]Jiale Ding, Yukai Huang, Dengquan Li
Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs. Circuits Syst. Signal Process. 41(12): 6632-6650 (2022) - [j18]Dengquan Li, Xin Zhao
Radio frequency analog-to-digital converters: Systems and circuits review. Microelectron. J. 119: 105331 (2022) - [j17]Yukai Huang, Jiale Ding, Dengquan Li
A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration. Microelectron. J. 122: 105394 (2022) - [j16]Henghui Mao, Dengquan Li
A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS. Microelectron. J. 122: 105395 (2022) - [j15]Maliang Liu
A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1091-1101 (2022) - [j14]Depeng Sun, Ruixue Ding
A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2672-2676 (2022) - [j13]Dengquan Li
A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1558-1562 (2022) - [c4]Tian Feng, Dengquan Li, Jiale Ding, Shubin Liu, Yi Shen, Zhangming Zhu:
A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower. ICTA 2022: 13-14 - 2021
- [j12]Lei Zhao, Dengquan Li
A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS. J. Circuits Syst. Comput. 30(8): 2150143:1-2150143:19 (2021) - [j11]Dengquan Li, Maliang Liu, Shubin Liu, Yuhua Liang, Ruixue Ding:
A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs. Microelectron. J. 114: 105114 (2021) - [j10]Zhangming Zhu
A TD-ADC for IR-UWB Radars With Equivalent Sampling Technology and 8-GS/s Effective Sampling Rate. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 888-892 (2021) - [c3]Jiaxin Liu, Dengquan Li, Yi Zhong
27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering. ISSCC 2021: 369-371 - 2020
- [j9]Dengquan Li
A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration. IEEE J. Solid State Circuits 55(11): 3051-3063 (2020) - [j8]Dengquan Li
An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS. IEEE Trans. Circuits Syst. 67-II(11): 2307-2311 (2020) - [j7]Maliang Liu
A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application. IEEE Trans. Circuits Syst. II Express Briefs 67-II(4): 650-654 (2020)
2010 – 2019
- 2019
- [j6]Dengquan Li
A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 16-20 (2019) - [c2]Dengquan Li, Jiaxin Liu
A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration. CICC 2019: 1-4 - 2018
- [j5]Rui Ma
A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS. Microelectron. J. 78: 63-72 (2018) - [j4]Dengquan Li
A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1524-1528 (2018) - [c1]Dengquan Li, Ruixue Ding, Zhangming Zhu, Yintang Yang:
A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation. APCCAS 2018: 53-56 - 2016
- [j3]Liang Zhang, Dengquan Li
A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS. J. Circuits Syst. Comput. 25(8): 1650084:1-1650084:11 (2016) - [j2]Dengquan Li
A background fast convergence algorithm for timing skew in time-interleaved ADCs. Microelectron. J. 47: 45-52 (2016) - 2015
- [j1]Dengquan Li
An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS. J. Circuits Syst. Comput. 24(6): 1550093:1-1550093:14 (2015)
Coauthor Index
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