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Ishan G. Thakkar
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2020 – today
- 2024
- [j12]Venkata Sai Praneeth Karempudi
, Janibul Bashir
An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects. ACM J. Emerg. Technol. Comput. Syst. 20(2): 6:1-6:34 (2024) - [j11]Salma Afifi
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(11): 3336-3347 (2024) - [c36]Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Oluwaseun Adewunmi Alo, Jeffrey Todd Hastings, Justin Scott Woods:
A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride Photonics. ISQED 2024: 1-8 - [c35]Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Adewunmi Alo, Ishan G. Thakkar:
A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators. ISQED 2024: 1-8 - [c34]Oluwaseun Adewunmi Alo, Sairam Sri Vatsavai, Ishan G. Thakkar:
Scaling Analog Photonic Accelerators for Byte-Size, Integer General Matrix Multiply (GEMM) Kernels. ISVLSI 2024: 409-414 - [i25]Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Adewunmi Alo, Ishan G. Thakkar:
A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators. CoRR abs/2402.03149 (2024) - [i24]Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar:
HEANA: A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference. CoRR abs/2402.03247 (2024) - [i23]Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Oluwaseun Adewunmi Alo, Jeffrey Todd Hastings, Justin Scott Woods:
A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride Photonics. CoRR abs/2402.11047 (2024) - [i22]Oluwaseun Adewunmi Alo, Sairam Sri Vatsavai, Ishan G. Thakkar:
Scaling Analog Photonic Accelerators for Byte-Size, Integer General Matrix Multiply (GEMM) Kernels. CoRR abs/2407.06134 (2024) - [i21]Salma Afifi, Ishan G. Thakkar, Sudeep Pasricha:
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks. CoRR abs/2407.12638 (2024) - 2023
- [c33]Ishan G. Thakkar
High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures. ACM Great Lakes Symposium on VLSI 2023: 545-550 - [c32]Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar, Sayed Ahmad Salehi, Jeffrey Todd Hastings:
SCONNA: A Stochastic Computing Based Optical Accelerator for Ultra-Fast, Energy-Efficient Inference of Integer-Quantized CNNs. IPDPS 2023: 546-556 - [c31]Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Jeffrey Todd Hastings:
A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits. ISQED 2023: 1-8 - [c30]Supreeth Mysore Shivanandamurthy, Sairam Sri Vatsavai, Ishan G. Thakkar, Sayed Ahmad Salehi:
AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning. ISQED 2023: 1-8 - [c29]Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar:
An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks. ISQED 2023: 1-8 - [c28]Sairam Sri Vatsavai, Ishan G. Thakkar:
A Bit-Parallel Deterministic Stochastic Multiplier. ISQED 2023: 1 - [i20]Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Jeffrey Todd Hastings:
A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits. CoRR abs/2301.13626 (2023) - [i19]Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar:
An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks. CoRR abs/2302.06405 (2023) - [i18]Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar, Sayed Ahmad Salehi, Jeffrey Todd Hastings:
SCONNA: A Stochastic Computing Based Optical Accelerator for Ultra-Fast, Energy-Efficient Inference of Integer-Quantized CNNs. CoRR abs/2302.07036 (2023) - [i17]Supreeth Mysore Shivanandamurthy, Sairam Sri Vatsavai, Ishan G. Thakkar, Sayed Ahmad Salehi:
AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning. CoRR abs/2302.07746 (2023) - [i16]Sairam Sri Vatsavai, Ishan G. Thakkar:
A Bit-Parallel Deterministic Stochastic Multiplier. CoRR abs/2302.08324 (2023) - [i15]Ishan G. Thakkar, Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi:
High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures. CoRR abs/2304.07608 (2023) - [i14]Venkata Sai Praneeth Karempudi, Ishan G. Thakkar, Jeffrey Todd Hastings:
A Silicon Nitride Microring Modulator for High-Performance Photonic Integrated Circuits. CoRR abs/2306.07238 (2023) - [i13]Venkata Sai Praneeth Karempudi, Janibul Bashir, Ishan G. Thakkar:
An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects. CoRR abs/2306.07241 (2023) - 2022
- [j10]Venkata Sai Praneeth Karempudi
Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study. ACM J. Emerg. Technol. Comput. Syst. 18(3): 45:1-45:36 (2022) - [j9]Amlan Ganguly
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion. IEEE Micro 42(3): 40-49 (2022) - [j8]Sairam Sri Vatsavai
Photonic Reconfigurable Accelerators for Efficient Inference of CNNs With Mixed-Sized Tensors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4337-4348 (2022) - [c27]Venkata Sai Praneeth Karempudi, Ishan G. Thakkar, Jeffrey Todd Hastings:
A Silicon Nitride Microring Based High-Speed, Tuning-Efficient, Electro-Refractive Modulator. iSES 2022: 307-311 - [i12]Sairam Sri Vatsavai, Ishan G. Thakkar:
Photonic Reconfigurable Accelerators for Efficient Inference of CNNs with Mixed-Sized Tensors. CoRR abs/2207.05278 (2022) - 2021
- [j7]Sai Vineel Reddy Chittamuru
Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 850-863 (2021) - [j6]Febin P. Sunny
ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1206-1219 (2021) - [c26]Bobby Bose, Ishan G. Thakkar:
Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs. ACM Great Lakes Symposium on VLSI 2021: 101-107 - [c25]Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi:
ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing. ISVLSI 2021: 200-205 - [c24]Venkata Sai Praneeth Karempudi, Shreyan Datta
Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic Unit. SenSys 2021: 628-634 - [c23]Sairam Sri Vatsavai, Ishan G. Thakkar:
Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing. VLSID 2021: 129-134 - [i11]Sairam Sri Vatsavai, Ishan G. Thakkar:
Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing. CoRR abs/2101.00557 (2021) - [i10]Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi:
ODIN: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-Situ Neural Network Processing in Phase Change RAM. CoRR abs/2103.03953 (2021) - [i9]Febin Sunny, Asif Mirza, Ishan G. Thakkar, Mahdi Nikdast, Sudeep Pasricha:
ARXON: A Framework for Approximate Communication over Photonic Networks-on-Chip. CoRR abs/2103.08828 (2021) - [i8]Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi:
ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing. CoRR abs/2105.12781 (2021) - [i7]Bobby Bose, Ishan G. Thakkar:
Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs. CoRR abs/2106.09308 (2021) - [i6]Venkata Sai Praneeth Karempudi, Febin Sunny, Ishan G. Thakkar, Sai Vineel Reddy Chittamuru, Mahdi Nikdast, Sudeep Pasricha:
Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study. CoRR abs/2110.06105 (2021) - 2020
- [c22]Febin Sunny, Asif Mirza, Ishan G. Thakkar, Sudeep Pasricha, Mahdi Nikdast:
LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip. ACM Great Lakes Symposium on VLSI 2020: 235-240 - [c21]Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar:
Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication. ACM Great Lakes Symposium on VLSI 2020: 247-252 - [c20]Chao-Hsuan Huang, Ishan G. Thakkar:
Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. ICCD 2020: 417-420 - [c19]Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar:
PROTEUS: Rule-Based Self-Adaptation in Photonic NoCs for Loss-Aware Co-Management of Laser Power and Performance. NOCS 2020: 1-8 - [i5]Febin Sunny, Asif Mirza, Ishan G. Thakkar, Sudeep Pasricha, Mahdi Nikdast:
LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip. CoRR abs/2002.11289 (2020) - [i4]Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar:
Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication. CoRR abs/2003.11895 (2020) - [i3]Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha, Sairam Sri Vatsavai, Varun Bhat:
Exploiting Process Variations to Secure Photonic NoC Architectures from Snooping Attacks. CoRR abs/2007.10454 (2020) - [i2]Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar:
PROTEUS: Rule-Based Self-Adaptation in Photonic NoCs for Loss-Aware Co-Management of Laser Power and Performance. CoRR abs/2008.07566 (2020) - [i1]Chao-Hsuan Huang, Ishan G. Thakkar:
Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. CoRR abs/2008.11367 (2020)
2010 – 2019
- 2019
- [c18]Chao-Hsuan Huang, Ishan G. Thakkar:
Mitigating Write Disturbance in Phase Change Memory Architectures. CASES (work in progress) 2019: 1-2 - [c17]Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi:
A scalable stochastic number generator for phase change memory based in-memory stochastic processing: work-in-progress. CODES+ISSS 2019: 6:1-6:2 - [c16]Venkata Sai Praneeth Karempudi, Ishan G. Thakkar:
Mitigating inter-channel crosstalk non-uniformity in microring filter arrays of photonic NoCs: work-in-progress. CODES+ISSS 2019: 8:1-8:2 - 2018
- [j5]Ishan G. Thakkar
DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1760-1773 (2018) - [j4]Sai Vineel Reddy Chittamuru
LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip. IEEE Trans. Multi Scale Comput. Syst. 4(4): 758-772 (2018) - [j3]Sai Vineel Reddy Chittamuru
HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 168-181 (2018) - [c15]Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat, Sudeep Pasricha:
SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures. DAC 2018: 81:1-81:6 - [c14]Sudeep Pasricha, Sai Vineel Reddy Chittamuru
Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-Chip. ACM Great Lakes Symposium on VLSI 2018: 317-322 - [c13]Ishan G. Thakkar, Sudeep Pasricha:
Mitigating the Energy Impacts of VBTI Aging in Photonic Networks-on-Chip Architectures with Multilevel Signaling. IGSC 2018: 1-7 - [c12]Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat:
Securing Photonic NoC Architectures from Hardware Trojans. NOCS 2018: 15:1-15:8 - 2017
- [c11]Ishan G. Thakkar, Sai Vineel Reddy Chittamuru
Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling. NOCS 2017: 4:1-4:8 - [c10]Sai Vineel Reddy Chittamuru
Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing. SLIP 2017: 1-8 - [c9]Ishan G. Thakkar, Sudeep Pasricha:
DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency. VLSID 2017: 41-46 - 2016
- [c8]Ishan G. Thakkar, Sai Vineel Reddy Chittamuru
Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling. CODES+ISSS 2016: 24:1-24:10 - [c7]Sai Vineel Reddy Chittamuru
PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs. DAC 2016: 39:1-39:6 - [c6]Sai Vineel Reddy Chittamuru
Process variation aware crosstalk mitigation for DWDM based photonic NoC architectures. ISQED 2016: 57-62 - [c5]Ishan G. Thakkar, Sai Vineel Reddy Chittamuru
Run-time laser power management in photonic NoCs with on-chip semiconductor optical amplifiers. NOCS 2016: 1-4 - [c4]Ishan G. Thakkar, Sai Vineel Reddy Chittamuru
A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects. SLIP 2016: 1:1-1:8 - [c3]Ishan G. Thakkar, Sudeep Pasricha:
Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures. VLSID 2016: 104-109 - 2015
- [j2]Ishan G. Thakkar, Sudeep Pasricha:
3-D WiRED: A Novel WIDE I/O DRAM With Energy-Efficient 3-D Bank Organization. IEEE Des. Test 32(4): 71-80 (2015) - [j1]Ishan G. Thakkar, Sudeep Pasricha:
3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead. IEEE Trans. Multi Scale Comput. Syst. 1(3): 168-184 (2015) - [c2]Ishan G. Thakkar, Sudeep Pasricha:
A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses. ICCD 2015: 467-470 - 2014
- [c1]Ishan G. Thakkar, Sudeep Pasricha:
3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time. ICCD 2014: 1-7
Coauthor Index
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last updated on 2024-12-05 21:39 CET by the dblp team
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