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Ziyad Hanna
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2010 – 2019
- 2015
- [c27]Ziyad Hanna:
Democratization of Formal Verification with Collective Intelligence. FMCAD 2015: 5 - 2014
- [c26]Ziyad Hanna:
Challenging problems in industrial formal verification. FMCAD 2014: 1 - 2012
- [c25]Jamil Mazzawi, Ziyad Hanna:
Formal Analysis of Security Data Paths in RTL Design. Haifa Verification Conference 2012: 7 - 2011
- [b1]Ziyad Hanna:
A symbolic execution framework for algorithm-level modelling and verification of computer microarchitecture. University of Oxford, UK, 2011
2000 – 2009
- 2009
- [c24]Ziyad Hanna, Thomas F. Melham:
A symbolic execution framework for algorithm-level modelling. HLDVT 2009: 94-99 - 2007
- [c23]Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna:
An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability. ATS 2007: 288-294 - [c22]Roberto Bruttomesso, Alessandro Cimatti
, Anders Franzén, Alberto Griggio
A Lazy and Layered SMT($\mathcal{BV}$) Solver for Hard Industrial Verification Problems. CAV 2007: 547-560 - [c21]Ziyad Hanna:
Abstract Modeling and Formal Verification of Microprocessors. CSR 2007: 23 - [c20]Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili:
Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. FMCAD 2007: 20-26 - [c19]Nachum Dershowitz, Ziyad Hanna, Alexander Nadel:
Towards a Better Understanding of the Functionality of a Conflict-Driven SAT Solver. SAT 2007: 287-293 - [i2]Jacob Katz, Ziyad Hanna, Nachum Dershowitz:
Space-Efficient Bounded Model Checking. CoRR abs/0710.4629 (2007) - 2006
- [c18]Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng
Generation of shorter sequences for high resolution error diagnosis using sequential SAT. ASP-DAC 2006: 25-29 - [c17]Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna:
Post-reboot Equivalence and Compositional Verification of Hardware. FMCAD 2006: 11-18 - [c16]Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
A Scalable Algorithm for Minimal Unsatisfiable Core Extraction. SAT 2006: 36-41 - [i1]Nachum Dershowitz, Ziyad Hanna, Alexander Nadel:
A Scalable Algorithm for Minimal Unsatisfiable Core Extraction. CoRR abs/cs/0605085 (2006) - 2005
- [c15]Jacob Katz, Ziyad Hanna, Nachum Dershowitz:
Space-Efficient Bounded Model Checking. DATE 2005: 686-687 - [c14]Zurab Khasidashvili, Alexander Nadel
Simultaneous SAT-Based Model Checking of Safety Properties. Haifa Verification Conference 2005: 56-75 - [c13]Nachum Dershowitz, Ziyad Hanna, Alexander Nadel:
A Clause-Based Heuristic for SAT Solvers. SAT 2005: 46-60 - [c12]Nachum Dershowitz, Ziyad Hanna, Jacob Katz:
Bounded Model Checking with QBF. SAT 2005: 408-414 - [c11]Marco Bozzano
Encoding RTL Constructs for MathSAT: a Preliminary Report. PDPAR@CAV 2005: 3-14 - 2004
- [j2]Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna:
A Signal Correlation Guided Circuit-SAT Solver. J. Univers. Comput. Sci. 10(12): 1629-1654 (2004) - [c10]Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna:
Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. ICCAD 2004: 58-65 - [c9]Yulik Feldman, Nachum Dershowitz, Ziyad Hanna:
Parallel Multithreaded Satisfiability Solver: Design and Implementation. PDMC 2004: 75-90 - 2003
- [j1]Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna:
Design automation with mixtures of proof strategies for propositional logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1042-1048 (2003) - [c8]Feng Lu, Li-C. Wang, Kwang-Ting Cheng
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. DAC 2003: 436-441 - [c7]Zurab Khasidashvili, Ziyad Hanna:
SAT-based methods for sequential hardware equivalence verification without synchronization. BMC@CAV 2003: 593-607 - 2002
- [c6]Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna:
A proof engine approach to solving combinational design automation problems. DAC 2002: 725-730 - [c5]Amnon Rosenmann, Ziyad Hanna:
Alignability equivalence of synchronous sequential circuits. HLDVT 2002: 111-114 - [c4]Zurab Khasidashvili, John Moondanos, Ziyad Hanna:
TRANS: efficient sequential verification of loop-free circuits. HLDVT 2002: 115-120 - [c3]Sasha Novakovsky, Shy Shyman, Ziyad Hanna:
High capacity and automatic functional extraction tool for industrial VLSI circuit designs. ICCAD 2002: 520-525 - 2001
- [c2]John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss:
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV 2001: 131-143 - [c1]Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna:
An enhanced cut-points algorithm in formal equivalence verification. HLDVT 2001: 171-176
Coauthor Index
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