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Satoshi Komatsu
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2020 – today
- 2023
- [c40]Kota Hara, Satoshi Komatsu:
A PVT Variation Dependencies of VCO in Frequency Locked Loop. ICECS 2023: 1-4
2010 – 2019
- 2018
- [c39]Shinya Ubukata, Satoshi Komatsu:
A Framework for Automatic Generation of Fully Synthesizable ADPLL. ICECS 2018: 57-60 - 2017
- [c38]Takumi Saito, Satoshi Komatsu:
A low-voltage hysteresis comparator for low power applications. ICECS 2017: 427-430 - [c37]Ryosuke Yumoto, Satoshi Komatsu:
Characteristics optimization of stochastic ADC and its automatic generation system. NEWCAS 2017: 89-92 - 2016
- [j12]Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. J. Electron. Test. 32(3): 257-271 (2016) - [j11]Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. IEICE Trans. Electron. 99-C(10): 1219-1225 (2016) - [c36]James S. Tandon, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada:
A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators. NEWCAS 2016: 1-4 - 2014
- [j10]Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada:
A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 777-780 (2014) - [j9]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(8): 1688-1698 (2014) - [c35]Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada:
A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. ATS 2014: 168-173 - [c34]James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada:
A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. ISCAS 2014: 93-96 - [c33]Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada:
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. ITC 2014: 1-10 - 2013
- [j8]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2458-2466 (2013) - [c32]Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC 2013: 255-260 - [c31]James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada:
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. CICC 2013: 1-4 - [c30]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD 2013: 69-76 - [c29]Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada:
A novel test structure for measuring the threshold voltage variance in MOSFETs. ITC 2013: 1-8 - 2012
- [c28]Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu
, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira:
A New Procedure for Measuring High-Accuracy Probability Density Functions. Asian Test Symposium 2012: 185-190 - [c27]Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Power integrity control of ATE for emulating power supply fluctuations on customer environment. ITC 2012: 1-10 - 2011
- [c26]Mohamed Abbas, Takahiro J. Yamaguchi, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada:
Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology. ICECS 2011: 220-223 - [c25]Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada:
An equivalent-time and clocked approach for continuous-time quantization. ISCAS 2011: 2529-2532 - [c24]Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu:
Application of a continuous-time level crossing quantization method for timing noise measurements. ITC 2011: 1-10 - 2010
- [c23]Mohamed Abbas, Kwang-Ting Cheng
An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. DATE 2010: 1755-1760
2000 – 2009
- 2009
- [j7]Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1464-1475 (2009) - [c22]Toru Nakura, Yutaro Tatemura, Görschwin Fey
SAT-based ATPG testing of inter- and intra-gate bridging faults. ECCTD 2009: 643-646 - [c21]Mohamed Abbas, Kwang-Ting Cheng
Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. ETS 2009: 107-112 - 2008
- [c20]Görschwin Fey
Targeting Leakage Constraints during ATPG. ATS 2008: 225-230 - [c19]Satoshi Komatsu:
VLSI Test Exercise Courses for Students in EE Department. ITC 2008: 1 - 2007
- [c18]Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita:
Protocol Transducer Synthesis using Divide and Conquer approach. ASP-DAC 2007: 280-285 - [c17]Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction. ATVA 2007: 553-563 - [c16]Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. IESS 2007: 121-134 - [c15]Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada:
VLSI CAD Education and Exercise Course with Public Domain Tools. MSE 2007: 111-112 - 2006
- [j6]Yu Liu, Satoshi Komatsu, Masahiro Fujita:
Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 1018-1026 (2006) - [j5]Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
Synchronization Verification in System-Level Design with ILP Solvers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3387-3396 (2006) - [j4]Yu Liu, Satoshi Komatsu, Masahiro Fujita:
The AMS Extension to System Level Design Language - SpecC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3397-3407 (2006) - [c14]Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Dynamically reconfigurable protocol transducer. FPT 2006: 341-344 - [c13]Satoshi Komatsu, Masahiro Fujita:
An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme. ISCAS 2006 - 2005
- [j3]Satoshi Komatsu, Masahiro Fujita:
Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3282-3289 (2005) - [c12]Yu Liu, Satoshi Komatsu, Masahiro Fujita:
AMS Extensions for Timed/Untimed System-Level Design Language. FDL 2005: 77-81 - [c11]Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. FPT 2005: 137-144 - [c10]Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
System level design language extensions for timed/untimed digital-analog combined system design. ACM Great Lakes Symposium on VLSI 2005: 130-133 - [c9]Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
Synchronization verification in system-level design with ILP solvers. MEMOCODE 2005: 121-130 - 2003
- [j2]Satoshi Komatsu, Masahiro Fujita:
Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3001-3008 (2003) - [j1]Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3192-3199 (2003) - [c8]Satoshi Komatsu, Masahiro Fujita:
Irredundant address bus encoding techniques based on adaptive codebooks for low power. ASP-DAC 2003: 9-14 - [c7]Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima:
Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. HICSS 2003: 279 - [c6]Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita:
Engineering Changes in Field Modifiable Architectures. MEMOCODE 2003: 87-94 - [c5]Tohru Ishihara
Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE 2003: 41-42 - 2002
- [c4]Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita:
Field modifiable architecture with FPGAs and its design methodology. FPT 2002: 382-385 - [c3]Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS 2002: 103-108
1990 – 1999
- 1999
- [c2]Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. Great Lakes Symposium on VLSI 1999: 368-371 - 1998
- [c1]Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. ASP-DAC 1998: 323-324
Coauthor Index
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