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Journal of Electronic Testing, Volume 29
Volume 29, Number 1, February 2013
- Vishwani D. Agrawal:
Editorial. 1-2 - New Editors, 2013. 3
- 2012 JETTA Reviewers. 5-6
- Test Technology Newsletter. 7-8
- Thelma Elita Colanzi, Wesley Klewerton Guez Assunção
, Daniela de Freitas Guilhermino Trindade, Carlos Alberto Zorzo, Silvia Regina Vergilio:
Evaluating Different Strategies for Testing Software Product Lines. 9-24 - Viktor Mashkov
Applying Petri Nets to Modeling of Many-Core Processor Self-Testing when Tests are Performed Randomly. 25-34 - Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults. 35-48 - Hyoung-Kook Kim, Laung-Terng Wang, Yu-Liang Wu, Wen-Ben Jone:
Testing of Synchronizers in Asynchronous FIFO. 49-72 - Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints. 73-86 - Wassim Mansour
SEU Fault-Injection in VHDL-Based Processors: A Case Study. 87-94 - Han Han, Houjun Wang, Shulin Tian, Na Zhang:
A New Analog Circuit Fault Diagnosis Method Based on Improved Mahalanobis Distance. 95-102 - Ozgur Sinanoglu
Eliminating the Timing Penalty of Scan. 103-114 - Xifeng Li, Yongle Xie:
Analog Circuits Fault Detection Using Cross-Entropy Approach. 115-120
Volume 29, Number 2, April 2013
- Vishwani D. Agrawal:
Editorial. 121 - Test Technology Newsletter. 123-124
- Dimitris Gizopoulos, Said Hamdioui, Hans A. R. Manhaeve:
Guest Editorial - Special Issue on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN). 125-126 - Olivier Héron, Clement Bertolini, Chiara Sandionigi, Nicolas Ventroux, François Marc:
On the Simulation of HCI-Induced Variations of IC Timings at High Level. 127-141 - Liang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis. 143-158 - Cristiana Bolchini
Self-Adaptive Fault Tolerance in Multi-/Many-Core Systems. 159-175 - Ismail Akturk, Ozcan Ozturk:
Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design. 177-184 - Natalja Kehl, Wolfgang Rosenstiel:
Circuit Level Concurrent Error Detection in FSMs. 185-192 - Amitabh Das, Jean DaRolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
Secure JTAG Implementation Using Schnorr Protocol. 193-209 - Salma Bergaoui, A. Wecxsteen, Régis Leveugle:
Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems. 211-222 - Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification. 223-236 - Ashok Kavithamani, Venugopal Manikandan, Nanjundappan Devarajan:
Soft Fault Classification of Analog Circuits Using Network Parameters and Neural Networks. 237-240 - Kanad Chakraborty, James E. Kelly, Brian P. Evans:
Novel Self-Timed, Pipelined Clock Scan Architecture. 241-247 - Zhichao Zhang, Yi Ren, Li Chen
A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients. 249-253
Volume 29, Number 3, June 2013
- Vishwani D. Agrawal:
Editorial. 255 - Test Technology Newsletter. 257
- Prashant D. Joshi, Massimo Violante:
Guest Editorial. 259-260 - Geunho Cho, Fabrizio Lombardi:
On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment. 261-273 - Yiwen Shi, Jennifer Dworak:
A Simulated Annealing Inspired Test Optimization Method for Enhanced Detection of Highly Critical Faults and Defects. 275-288 - Julio César Vázquez, Víctor H. Champac, Jorge Semião
Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion. 289-299 - Enrico Costenaro, Dan Alexandrescu, Kader Belhaddad, Michael Nicolaidis:
A Practical Approach to Single Event Transient Analysis for Highly Complex Design. 301-315 - Sreenivas Gangadhar, Spyros Tragoudas:
A Probabilistic Approach to Diagnose SETs in Sequential Circuits. 317-330 - Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre:
A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic. 331-340 - Monica Alderighi
A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs. 341-350 - Naghmeh Karimi, Michail Maniatakos
On the Impact of Performance Faults in Modern Microprocessors. 351-366 - Mathilde Soucarros, Jessy Clédière
Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor. 367-381 - Thierry Bonnoit
Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study. 383-400 - Daniele Rossi
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. 401-413 - Yusuke Fukushima, Masaru Fukushi, Ikuko Eguchi Yairi
A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip. 415-429 - Khalid Latif, Amir-Mohammad Rahmani, Ethiopia Nigussie, Tiberiu Seceleanu
Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip. 431-452
Volume 29, Number 4, August 2013
- Vishwani D. Agrawal:
Editorial. 453 - Test Technology Newsletter. 455-456
- Claude Thibeault, Yassine Hariri, Syed Rafay Hasan, Christelle Hobeika, Yvon Savaria, Yves Audet, Fatima Zahra Tazi:
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design. 457-471 - Suraj Sindia, Vishwani D. Agrawal:
Neural Network Guided Spatial Fault Resilience in Array Processors. 473-483 - Mohammad Hossein Neishaburi, Zeljko Zilic:
A Fault Tolerant Hierarchical Network on Chip Router Architecture. 485-497 - Nima Aghaee
Process-Variation and Temperature Aware SoC Test Scheduling Technique. 499-520 - Lars Schor, Iuliana Bacivarov, Hoeseok Yang
Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs. 521-535 - Rahebeh Niaraki Asli, Saeideh Shirinzadeh:
High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design. 537-544 - Kazuteru Namba, Takashi Katagiri, Hideo Ito:
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop. 545-554 - Yongcai Ao, Yibing Shi, Wei Zhang, Yanjun Li:
An Approximate Calculation of Ratio of Normal Variables and Its Application in Analog Circuit Fault Diagnosis. 555-565 - Min Li, Weiming Xian, Bing Long, Houjun Wang:
Prognostics of Analog Filters Based on Particle Filters Using Frequency Features. 567-584 - Tie-Bin Wu, Heng-Zhu Liu, Peng-Xia Liu, Dong-Sheng Guo, Hai-Ming Sun:
A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic. 585-600 - Valentin Gherman, Samuel Evain, Yannick Bonhomme:
Memory Reliability Improvement Based on Maximized Error-Correcting Codes. 601-608 - Yi Ren, Shuting Shi, Li Chen
Correlation of Heavy-Ion and Laser Testing on a DC/DC PWM Controller. 609-616
Volume 29, Number 5, October 2013
- Vishwani D. Agrawal:
Editorial. 617 - Test Technology Newsletter. 619-620
- Sandip Ray, Jay Bhadra, Magdy S. Abadir, Li-C. Wang
Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs. 621-623 - Lung-Jen Lee:
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction. 625-634 - Marcelo Sousa, Alper Sen:
LLVMVF: A Generic Approach for Verification of Multicore Software. 635-646 - Nicola Bombieri
On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation. 647-667 - Lingyi Liu, Shobha Vasudevan:
Automatic Generation of System Level Assertions from Transaction Level Models. 669-684 - Yanyan Gao, Xi Li:
A Semantics-based Translation Method for Automated Verification of SystemC TLM Designs. 685-695 - Gürkan Uygur, Sebastian Sattler:
A Novel Formalism for Partially Defined Asynchronous Feedback Digital Circuits. 697-714 - Kusum Lata
Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces. 715-740
Volume 29, Number 6, December 2013
- Vishwani D. Agrawal:
Editorial. 741-742 - Test Technology Newsletter. 743-744
- Sukeshwar Kannan, Kaushal Kannan, Bruce C. Kim, Friedrich Taenzler, Richard Antley, Ken Moushegian, Kenneth M. Butler, Doug Mirizzi:
Physics-Based Low-Cost Test Technique for High Voltage LDMOS. 745-762 - Noor M. Nayeem, Jacqueline E. Rice:
Online Testable Approaches in Reversible Logic. 763-778 - Cristiana Bolchini
Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms. 779-793 - Stefanos Valadimas, Yiorgos Tsiatouhas
Effective Timing Error Tolerance in Flip-Flop Based Core Designs. 795-804 - Alexandros Vavousis, Andreas Apostolakis, Mihalis Psarakis:
A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration. 805-823 - Felipe Restrepo-Calle
Selective SWIFT-R - A Flexible Software-Based Technique for Soft Error Mitigation in Low-Cost Embedded Systems. 825-838 - Jefferson P. Koppe, Elias P. Duarte Jr., Luis C. E. Bona
MoDiVHA: A Hierarchical Strategy for Distributed Test Assignment. 839-847 - Tie-Bin Wu, Heng-Zhu Liu, Peng-Xia Liu:
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding. 849-859 - Likun Xia, Muhammad Umer Farooq
Survey and Evaluation of Automated Model Generation Techniques for High Level Modeling and High Level Fault Modeling. 861-877 - Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. 879-892 - Tian Xia, Rohit Shetty, Timothy Platt, Mustapha Slamani:
Low Cost Time Efficient Multi-tone Test Signal Generation Using OFDM Technique. 893-901 - Shlomi Dolev
Preserving Hamming Distance in Arithmetic and Logical Operations. 903-907
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