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23rd PATMOS 2013: Karlsruhe, Germany
- 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Karlsruhe, Germany, September 9-11, 2013. IEEE 2013
Keynotes
- Bashir M. Al-Hashimi:
Hardware reliability of embedded systems: Are we there yet? 1 - Radu Marculescu:
Design of future integrated systems: A cyber-physical systems approach. 1
Sub-Threshold Operation and Variability
- Nathaniel A. Conos, Saro Meguerdichian, Sheng Wei, Miodrag Potkonjak:
Maximizing yield in Near-Threshold Computing under the presence of process variation. 1-8 - Marc Pons
, Jean-Luc Nagel, Daniel Séverac, Marc-Nicolas Morgan, Daniel Sigg, Pierre-François Rüedi, Christian Piguet:
Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation. 9-15 - Alex A. Birklykke, Peter Koch
Empirical verification of fault models for FPGAs operating in the subcritical voltage region. 16-23 - Frank P. Burns, Abdullah Baz
Variability analysis of self-timed SRAM robustness. 24-31 - Daniele Bortolotti
A variation tolerant architecture for ultra low power multi-processor cluster. 32-38 - Kjell O. Jeppson:
A learning tool MOSFET model: A stepping-stone from the square-law model to BSIM4. 39-44
Towards Cross Abstraction Level Power Closure
- Juergen Karmann, Wolfgang Ecker:
The semantic of the power intent format UPF: Consistent power modeling from system level to implementation. 45-50 - Lars Kosmann, Daniel Lorenz, Axel Reimer, Wolfgang Nebel:
Enabling energy-aware design decisions for behavioural descriptions containing black-box IP-components. 51-58 - Gregor Nitsche, Kim Grüttner, Wolfgang Nebel:
Power contracts: A formal way towards power-closure?! 59-66 - Joakim Urdahl, Shrinidhi Udupi, Dominik Stoffel, Wolfgang Kunz:
Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design. 67-74
System-level Power and Thermal Management
- Vishwa Goudar, Zhi Ren, Paul Brochu, Qibing Pei
Optimizing the configuration and control of a novel human-powered energy harvesting system. 75-82 - Filippo Casamassima, Elisabetta Farella
Power saving policies for multipurpose WBAN. 83-90 - Sascha Bischoff, Andreas Hansson, Bashir M. Al-Hashimi:
Applying of Quality of Experience to system optimisation. 91-98 - Francesco Beneventi, Andrea Bartolini
On-line thermal emulation: How to speed-up your thermal controller design. 99-106 - Marco Cazzaniga
Evaluating the impact of substrate on power integrity in industrial microcontrollers. 107-111 - Vasily G. Moshnyaga:
An assessment of software lifecycle energy. 112-119
Microarchitectures and NoCs
- Xinghua Yang, Fei Qiao, Chang Liu, Huazhong Yang:
Design of variable latency adder based on present and transitional states prediction. 120-125 - Thomas Polzer, Andreas Steininger
SET propagation in micropipelines. 126-133 - Michael Vonbun, Stefan Wallentowitz
Evaluation of hop count advantages of network-coded 2D-mesh NoCs. 134-141 - Ewerton Daniel de Lima, Tiago Cariolano de Souza Xavier
Compiling for performance and power efficiency. 142-149
Circuit Monitoring and Characterization
- Nasim Pour Aryan, Georg Georgakos, Doris Schmitt-Landsiedel:
Reliability monitoring of digital circuits by in situ timing measurement. 150-156 - Rodrigo Possamai Bastos, Frank Sill Torres
A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. 157-163 - Thomas Polzer, Andreas Steininger
Metastability characterization for muller C-elements. 164-171
Simulation and Modeling
- Fabian Mischkalla, Wolfgang Müller:
Efficient power Intent validation using loosely-timed simulation models. 172-179 - Junghyun Lee, Yungseon Eo:
An efficient eye-diagram determination technique for multi-coupled interconnect lines. 185-190 - Thomas Ducroux, Germain Haugou, Vincent Risson, Pascal Vivet
Fast and accurate power annotated simulation: Application to a many-core architecture. 191-198
Dynamic Voltage and Frequency Scaling
- Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné
Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing. 199-206 - Maurício Altieri, Warody Lombardi, Diego Puschini, Suzanne Lesecq:
Coupled voltage and frequency control for DVFS management. 207-214 - Christoph W. Kessler, Nicolas Melot, Patrick Eitschberger, Jörg Keller:
Crown scheduling: Energy-efficient resource allocation, mapping and discrete frequency scaling for collections of malleable streaming tasks. 215-222
Low Power Design Methods in Emerging Technologies
- Sandeep Miryala, Andrea Calimera
Power modeling and characterization of Graphene-based logic gates. 223-226 - Alessandro Magnani
Dynamic electrothermal macromodeling techniques for thermal-aware design of circuits and systems. 227-230 - Davide Zoni
Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations. 231-234
Poster Session
- Carlos Gomez, Julien DeAntoni
Power consumption analysis using multi-view modeling. 235-238 - Alessandro Sassone, Massimo Petricca, Massimo Poncino, Enrico Macii:
A fully standard-cell delay measurement circuit for timing variability detection. 239-242 - Georgios Tzimpragos, Christoforos Kachris, Dimitrios Soudris, Ioannis Tomkos
Automatic implementation of low-complexity QC-LDPC encoders. 243-246 - H. Ye, Lionel Lacassagne, Joël Falcou, Daniel Etiemble, Laurent Cabaret
High level tranforms toreduce energy consumption of signal and image processing operators. 247-254 - Waqaas Munawar, Jian-Jia Chen
Peak power demand analysis and reduction by using battery buffers for monotonic controllers. 255-258 - Georgios Tzimpragos, Christoforos Kachris, Dimitrios Soudris
Automatic implementation of low-complexity QC-LDPC encoders. 257-260 - Andrea Manuzzato, Fabio Campi, Valentino Liberali
Design methodology for low-power embedded microprocessors. 259-264 - Massimo Petricca, Donghwa Shin, Alberto Bocca, Alberto Macii
A framework with temperature-aware accuracy levels for battery modeling from datasheets. 265-268
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