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18th LATS 2017: Bogotá, Colombia
- 18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017. IEEE 2017, ISBN 978-1-5386-0415-1
- Alberto Bosio, Arnaud Virazel
, Patrick Girard
Approximate computing: Design & test for integrated circuits. 1 - Nandeesha Veeranna, Benjamin Carrión Schäfer:
Efficient behavioral intellectual properties source code obfuscation for high-level synthesis. 1-6 - Vaibhav Venugopal Rao, Ioannis Savidis:
Protecting analog circuits with parameter biasing obfuscation. 1-6 - André Lucas Chinazzo, Paulo César Comassetto de Aguirre
Low cost automatic test vector generation for structural analog testing. 1-4 - Satoshi Ohtake, Daichi Shimazu:
An approach to LFSR-based X-masking for built-in self-test. 1-4 - Luis Alberto Contreras Benites, Fernanda Lima Kastensmidt
Fault injection methodology for single event effects on clock-gated ASICs. 1-4 - Gabriel S. Porto, Paulo F. Butzen
Exploring BDDs to reduce test pattern set. 1-4 - Felipe Restrepo-Calle
An effective strategy for selective hardening of software. 1-6 - Alejandro David Velasco, Bartolomeo Montrucchio, Maurizio Rebaudengo:
TMR technique for mutex kernel data structures. 1-6 - Andrea Floridia, R. Margelli, Ernesto Sánchez:
On the development of a high-level fault simulator for the analysis of performance faults on speculative modules. 1-6 - Fabio Benevenuti, Fernanda Lima Kastensmidt
Evaluation of fault attack detection on SRAM-based FPGAs. 1-6 - M. Solinas, Alexandre Coelho, Juan A. Fraire
Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs. 1-4 - Vinicius Martins, Jiang Chau Wang
Mixed signal verification to avoid integration mismatch in complex SoCs. 1-6 - Ismael Lomeli-Illescas, Sergio A. Solis-Bustos, José Ernesto Rayas-Sánchez
Analysis of the implications of stacked devices in nano-scale technologies for analog applications. 1-4 - Carlos J. González
Evaluation of a mixed-signal design diversity system under radiation effects. 1-6 - Jan Burchard, Felix Neubauer, Pascal Raiola
Evaluating the effectiveness of D-chains in SAT-based ATPG. 1-6 - Toral Shah
Testing multiple stuck-at faults of ROBDD based combinational circuit design. 1-6 - Oscar Acevedo Patino, Juan Carlos Martínez Santos
Physical-aware pattern selection for stuck-at faults. 1-5 - Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac:
Analysis of short defects in FinFET based logic cells. 1-6 - Felix Mühlbauer
Handling manufacturing and aging faults with software-based techniques in tiny embedded systems. 1-6 - Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja:
Identifying high variability speed-limiting paths under aging. 1-6 - Oscar Acevedo
LFSR characteristic polynomial and phase shifter computation for two-dimensional test set generation. 1-6 - Gaiping An, Riccardo Cantoro
On the detection of board delay faults through the execution of functional programs. 1-6 - Enea Bagalini, Jacopo Sini
An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard. 1-6 - Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Post-silicon observability enhancement with topology based trace signal selection. 1-6 - Felipe G. H. Leite, Roberto B. B. Santos, Nilberto H. Medina, Vitor A. P. Aguiar
Ionizing radiation effects on a COTS low-cost RISC microcontroller. 1-4 - Thierry Bonnoit
SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core. 1-4 - Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt
Evaluating the behavior of successive approximation algorithms under soft errors. 1-6 - Matheus Berger Oliveira, Joao de Moraes, Sérgio Luis Cechin, Taisy Silva Weber, Joao Netto:
Practical experience designing and debugging an FPGA for a real-time ethernet industrial bus. 1-6 - Paolo Bernardi
A DMA and CACHE-based stress schema for burn-in of automotive microcontroller. 1-6 - Ronaldo Milfont, Paulo Cortez
Analysis of routing algorithms generation for irregular NoC topologies. 1-5 - Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis:
MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips. 1-4 - Israel C. Lopes, Fernanda Lima Kastensmidt
SEU susceptibility analysis of a feedforward neural network implemented in a SRAM-based FPGA. 1-6 - Jose Isaza-Gonzalez, Alejandro Serrano-Cases
Contrast of a HDL model and COTS version of a microprocessor for soft-error testing. 1-6 - Paulo Ricardo Cechelero Villa, Roger C. Goerl, Fabian Vargas, Leticia B. Poehls, Nilberto H. Medina
Analysis of single-event upsets in a Microsemi ProAsic3E FPGA. 1-4
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