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Vaibhav Venugopal Rao
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2020 – today
- 2024
- [c9]Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis:
DNA: DC Nodal Analysis Attack for Analog Circuits. ISCAS 2024: 1-5 - 2023
- [j2]Vaibhav Venugopal Rao
, Kyle Juretus
Hidden Costs of Analog Deobfuscation Attacks. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1802-1815 (2023) - 2022
- [c8]Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis:
Practical Performance of Analog Attack Techniques. HOST 2022: 153-156 - [c7]Vaibhav Venugopal Rao, Avesta Sasan, Ioannis Savidis:
Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits. ISQED 2022: 1-7 - 2021
- [j1]Vaibhav Venugopal Rao
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2013-2026 (2021) - 2020
- [c6]Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis:
Security Vulnerabilities of Obfuscated Analog Circuits. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c5]Kyle Juretus, Vaibhav Venugopal Rao, Ioannis Savidis:
Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies. ACM Great Lakes Symposium on VLSI 2019: 483-488 - [c4]Vaibhav Venugopal Rao, Ioannis Savidis:
Mesh Based Obfuscation of Analog Circuit Properties. ISCAS 2019: 1-5 - 2018
- [c3]Vaibhav Venugopal Rao, Ioannis Savidis:
Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory. APCCAS 2018: 102-106 - 2017
- [c2]Vaibhav Venugopal Rao, Ioannis Savidis:
Parameter biasing obfuscation for analog IP protection. HOST 2017: 161 - [c1]Vaibhav Venugopal Rao, Ioannis Savidis:
Protecting analog circuits with parameter biasing obfuscation. LATS 2017: 1-6
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