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15. ACM Great Lakes Symposium on VLSI 2005: Chicago, Illinois, USA
- John C. Lach, Gang Qu, Yehea I. Ismail:
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005. ACM 2005, ISBN 1-59593-057-4
Plenary session
- Florentin Dartu, Anirudh Devgan, Noel Menezes:
Variability modeling and variability-aware design in deep submicron integrated circuits. 1 - Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny:
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. 2-7 - Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas:
Low power test generation for path delay faults using stability functions. 8-12
Interconnect
- Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail:
Physical limitations on the bit-rate of on-chip interconnects. 13-19 - Vasilis F. Pavlidis, Eby G. Friedman:
Interconnect delay minimization through interlayer via placement in 3-D ICs. 20-25 - Syed M. Alam, Donald E. Troxel, Carl V. Thompson:
Thermal aware cell-based full-chip electromigration reliability analysis. 26-31 - Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
Accounting for the skin effect during repeater insertion. 32-37 - Gerald G. Lopez
, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti:
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. 38-43
Computer architecture
- Gang Wang, Wenrui Gong, Ryan Kastner:
Instruction scheduling using MAX-MIN ant system optimization. 44-49 - Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen:
A unified processor architecture for RISC & VLIW DSP. 50-55 - Kimish Patel, Enrico Macii, Massimo Poncino:
Zero clustering: an approach to extend zero compression to instruction caches. 56-59 - Alireza Hodjat, David Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede:
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. 60-63 - Shyamkumar Thoziyoor, Jay B. Brockman, Daniel Rinzler:
PIM lite: a multithreaded processor-in-memory prototype. 64-69
Poster session 1
- Tian Xia, Peilin Song, Hao Zheng:
Characterizing the VCO jitter due to the digital simultaneous switching noise. 70-73 - Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact minimum-width transistor placement without dual constraint for CMOS cells. 74-77 - Vishal Suthar, Shantanu Dutt:
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. 78-83 - Xiren Wang, Wenjian Yu, Zeyi Wang, Xianlong Hong:
An improved direct boundary element method for substrate coupling resistance extraction. 84-87 - Haralampos-G. D. Stratigopoulos, Yiorgos Makris
Generating decision regions in analog measurement spaces. 88-91 - Ozcan Ozturk, Mahmut T. Kandemir:
Integer linear programming based energy optimization for banked DRAMs. 92-95 - Amit Jain, David T. Blaauw:
Slack borrowing in flip-flop based sequential circuits. 96-101 - Eugene Goldberg:
On equivalence checking and logic synthesis of circuits with a common specification. 102-107 - Rui Tang, Fengming Zhang, Yong-Bin Kim:
Quantum-dot cellular automata SPICE macro model. 108-111 - Nirmal Ramalingam, Sanjukta Bhanja:
Causal probabilistic input dependency learning for switching model in VLSI circuits. 112-115 - Zhiyuan Yan, Dilip V. Sarwate:
Area-efficient two-dimensional architectures for finite field inversion and division. 116-121 - Jaehong Ko, Wookwan Lee, Soo-Won Kim:
2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design. 122-125 - Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
The oct-touched tile: a new architecture for shape-based routing. 126-129 - Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
System level design language extensions for timed/untimed digital-analog combined system design. 130-133 - Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi:
Noise-tolerant high fan-in dynamic CMOS circuit design. 134-137 - Lei Yang, Cherry Wakayama, Chuanjin Richard Shi:
Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer. 138-142 - Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou:
Improved multilevel routing with redundant via placement for yield and reliability. 143-146 - Hui Qin, Tsutomu Sasao, Yukihiro Iguchi:
An FPGA design of AES encryption circuit with 128-bit keys. 147-151 - Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Sun Jhang, Jeong-A Lee, Dong-Soo Har:
High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion. 152-155 - Rong Liu, Sheqin Dong, Xianlong Hong:
Fixed-outline floorplanning based on common subsequence. 156-159 - Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto
Interconnect capacitance extraction for system LCD circuits. 160-163 - Ying Yang, Zine-Eddine Abid, Wei Wang:
Two-prime RSA immune cryptosystem and its FPGA implementation. 164-167 - Sushanta K. Mandal
A simple wide-band compact model and parameter extraction using particle swarm optimization of on-chip spiral inductors for silicon RFICs. 168-171 - Yulei Weng, Alex Doboli:
Digital cell macro-model with regular substrate template and EKV based MOSFET model. 172-175
Testing
- Vishnu C. Vimjam, Manan Syal, Michael S. Hsiao:
Untestable fault identification through enhanced necessary value assignments. 176-181 - Stelios Neophytou, Maria K. Michael, Spyros Tragoudas:
Test set enhancement for quality transition faults using function-based methods. 182-187 - Hamidreza Hashempour, Fabrizio Lombardi:
Two dimensional reordering of functional test data for compression by ATE. 188-192 - Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour:
Diagnosing multiple transition faults in the absence of timing information. 193-196 - Franco Fummi, Cristina Marconcini, Graziano Pravadelli:
An EFSM-based approach for functional ATPG. 197-200
Nano and Emerging Technologies
- Vamsi Vankamamidi, Marco Ottavi
Tile-based design of a serial memory in QCA. 201-206 - Kuan Zhou, John F. McDonald:
Multi-GHz SiGe design methodologies for reconfigurable computing. 207-212 - Paul Beckett:
Low-power circuits using dynamic threshold devices. 213-216 - Brian Stephen Smith, Sung Kyu Lim
QCA channel routing with wire crossing minimization. 217-220 - Qinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai:
A new algorithm for layout of dark field alternating phase shifting masks. 221-224 - Vida Ilderem:
Research and development for seamless mobility. 225
High-level low power design I
- Sookyoung Kim, Thomas L. Martin:
DIP: a double-interval-based dynamic voltage scaling scheme for dynamic priority-based task scheduling systems. 226-231 - Liang Deng, Martin D. F. Wong
Energy optimization in memory address bus structure for application-specific systems. 232-237 - Somsubhra Mondal, Seda Ogrenci Memik:
Fine-grain leakage optimization in SRAM based FPGAs. 238-243 - Yuantao Peng, Xun Liu:
A sensitivity analysis of low-power repeater insertion. 244-247
Verification
- Ronald P. Lajaunie, Michael S. Hsiao:
An effective and efficient ATPG-based combinational equivalence checker. 248-253 - Kameshwar Chandrasekar, Michael S. Hsiao:
Forward image computation with backtracing ATPG and incremental state-set construction. 254-259 - Ghiath Al Sammane, Dominique Borrione, Remy Chevallier:
Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. 260-263 - Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler:
Utilizing don't care states in SAT-based bounded sequential problems. 264-269
High-level low power design II
- Ozcan Ozturk, Mahmut T. Kandemir:
Energy management in software-controlled multi-level memory hierarchies. 270-275 - Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino:
Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors. 276-281 - Gokhan Memik, Mahmut T. Kandemir, Arindam Mallik:
Load elimination for low-power embedded processors. 282-285 - Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu:
An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. 286-290 - Zhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto:
A VLSI array processing oriented fast fourier transform algorithm and hardware implementation. 291-295
Computer-aided design (CAD)
- Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi:
A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. 296-301 - Cristiano Forzan, Davide Pandini:
A complete methodology for an accurate static noise analysis. 302-307 - Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
A new approach to the use of satisfiability in false path detection. 308-311 - Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown:
Optimization objectives and models of variation for statistical gate sizing. 313-316 - Shahin Nazarian, Massoud Pedram, Emre Tuncer:
An empirical study of crosstalk in VDSM technologies. 317-322
Poster session 2
- Kuan Jen Lin, Shih Hao Huang, Shih Wen Chen
A hardware/software codesign approach for programmable IO devices. 323-327 - Srivathsan Krishnamohan, Nihar R. Mahapatra:
Analysis and design of soft-error hardened latches. 328-331 - Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska:
Clock skew bounds estimation under power supply and process variations. 332-336 - João Daniel Togni, Renato P. Ribas, Maria Lúcia Blanck Lisbôa, André Inácio Reis:
Tool integration using the web-services approach. 337-340 - Lin Yuan, Gang Qu, Ankur Srivastava
VLSI CAD tool protection by birthmarking design solutions. 341-344 - Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Eugene A. Feinberg:
A continuous time markov decision process based on-chip buffer allocation methodology. 345-348 - Amir Fijany, Farrokh Vatan, Mohammad M. Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil:
The G4-FET: a universal and programmable logic gate. 349-352 - Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin:
Using data compression in an MPSoC architecture for improving performance. 353-356 - Fei Hu, Vishwani D. Agrawal:
Dual-transition glitch filtering in probabilistic waveform power estimation. 357-360 - Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri:
SOFTENIT: a methodology for boosting the software content of system-on-chip designs. 361-366 - Pietro Babighian, Luca Benini, Alberto Macii
Low-overhead state-retaining elements for low-leakage MTCMOS design. 367-370 - Hamidreza Hashempour, Luca Schiano, Fabrizio Lombardi:
Enhancing error resilience for reliable compression of VLSI test data. 371-376 - Prassanna Sithambaram, Alberto Macii
Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs. 377-380 - Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge:
Total leakage optimization strategies for multi-level caches. 381-384 - Gaurav Gulati, Erik Brunvand:
Design of a cell library for asynchronous microengines. 385-389 - Amitava Bhaduri, Ranga Vemuri
Moment-driven coupling-aware routing methodology. 390-395 - Johannes Grad, James E. Stine:
New algorithms for carry propagation. 396-399 - Youngsik Kim, Parija Sule, Nazanin Mansouri:
Exploiting PSL standard assertions in a theorem-proving-based verification environment. 400-403 - Junwei Zhou, Andrew J. Mason:
Increasing design space of the instruction queue with tag coding. 404-407 - Ali Bastani, Charles A. Zukowski:
Characterization of monotonic static CMOS gates in a 65nm technology. 408-411 - Srivathsan Krishnamohan, Nihar R. Mahapatra:
An analysis of the robustness of CMOS delay elements. 412-415 - Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
A first look at the interplay of code reordering and configurable caches. 416-421 - Abdallah Merhebi, Otmane Aït Mohamed:
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks. 422-425 - Soroush Abbaspour, Hanif Fatemi, Massoud Pedram:
VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. 426-430
VLSI circuit design
- Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen:
1-V 7-mW dual-band fast-locked frequency synthesizer. 431-435 - Srivathsan Krishnamohan, Nihar R. Mahapatra:
Increasing the energy efficiency of pipelined circuits via slack redistribution. 436-441 - Bahar Jalali Farahani, Mohammed Ismail:
Adaptive digital techniques to suppress quantization noise of Sigma Delta analog to digital converters. 442-445
Routing
- Ajay Joshi, Jeffrey A. Davis:
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. 446-451 - Balasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri:
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip. 452-457 - Jacob R. Minz, Sung Kyu Lim
3D module placement for congestion and power noise reduction. 458-461
Circuit-level low power design
- Himanshu Kaul, Dennis Sylvester:
A novel buffer circuit for energy efficient signaling in dual-VDD systems. 462-467 - Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy:
Energy recovery clocked dynamic logic. 468-471 - Stephen C. Terry, Mohammad M. Mojarradi, Benjamin J. Blalock, Jesse A. Richmond:
Adaptive gate biasing: a new solution for body-driven current mirrors. 472-477 - Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi:
A high speed and leakage-tolerant domino logic for high fan-in gates. 478-481
Placement
- Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. 482-487 - Qinghua Liu, Malgorzata Marek-Sadowska:
A congestion-driven placement framework with local congestion prediction. 488-493 - Meng-Chiou Wu, Rung-Bin Lin:
Reticle floorplanning of flexible chips for multi-project wafers. 494-497 - Qingzhou (Ben) Wang, Devang Jariwala, John Lillis:
A study of tighter lower bounds in LP relaxation based placement. 498-502
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