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Chih-Wei Liu
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2020 – today
- 2024
- [c46]Tesheng Hsiao, Chih-Wei Liu:
Motion Controller Design with Automatic Loop Shaping and Minimum Tracking Errors. ACC 2024: 5226-5231 - 2022
- [j23]Faa-Jeng Lin
, Chih-Wei Liu, Po-Lun Wang:
Voltage Control of IPMSM Servo Drive in Constant Power Region With Intelligent Parameter Estimation. IEEE Access 10: 99243-99256 (2022) - 2021
- [j22]Chun-Hsun Wu, Bu-Wei Chen, Wei-Hung Ko, Chih-Wei Liu, Le-Ren Chang-Chien:
Phase sequence interchange scheme for suppressing transient cross regulation on the compensator controlled and non-compensator controlled single-inductor dual-output buck converter. IET Circuits Devices Syst. 15(7): 657-669 (2021) - [j21]Chih-Wei Liu
Area Efficient High-Performance Digitally Controlled Power Management Unit. IEEE Trans. Ind. Electron. 68(3): 2437-2446 (2021) - [c45]Ming-Chun Hsyu, Chih-Wei Liu, Chao-Hung Chen, Chao-Wei Chen, Wen-Chia Tsai:
CSAnet: High Speed Channel Spatial Attention Network for Mobile ISP. CVPR Workshops 2021: 2486-2493 - 2020
- [j20]Chih-Wei Liu
Auto-tuning charge balance control for improving transient response on buck converter. Int. J. Circuit Theory Appl. 48(6): 965-979 (2020) - [c44]Chih-Wei Liu, Le-Ren Chang-Chien:
Pipeline Signal Process Scheme for Saving Power Module Controllers in Power Management Unit. ISCAS 2020: 1-4 - [c43]Chih-Wei Liu, Jia-Yu Wu, Kang-Chun Huang:
A Low Latency NN-Based Cyclic Jacobi EVD Processor for DOA Estimation in Radar System. ISCAS 2020: 1-5 - [c42]Hong-Ke Lin, Pin-Han Lin, Chih-Wei Liu:
Design of a High-Throughput and Area-Efficient Ultra-Long FFT Processor. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [j19]Chih-Wei Liu
FFT-Based Multirate Signal Processing for 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 878-882 (2019) - [c41]Chia-Kai Chan, Hong-Ke Lin, Chih-Wei Liu:
High-Throughput 64K-point FFT Processor for THz Imaging Radar System. VLSI-DAT 2019: 1-4 - [c40]Ya-Chin Chung, Po-Hsiang Cheng, Chih-Wei Liu:
Energy Efficient CNN Inference Accelerator Using Fast Fourier Transform. VLSI-DAT 2019: 1-4 - 2018
- [j18]Chih-Wei Liu, Shao-Kang Lo, Ai-Yun Hsieh, Yujong Hwang
Effects of banner Ad shape and the schema creating process on consumer internet browsing behavior. Comput. Hum. Behav. 86: 9-17 (2018) - 2017
- [j17]Chih-Wei Liu, Ai-Yun Hsieh, Shao-Kang Lo, Yujong Hwang
What consumers see when time is running out: Consumers' browsing behaviors on online shopping websites when under time pressure. Comput. Hum. Behav. 70: 391-397 (2017) - 2016
- [j16]Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou
A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-Aid Systems. IEEE ACM Trans. Audio Speech Lang. Process. 24(8): 1380-1392 (2016) - [j15]Chih-Wei Liu, Shih-Hao Ou, Kuo-Chiang Chang, Tsung-Ching Lin, Shin-Kai Chen:
A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor. IEEE Trans. Computers 65(4): 1158-1164 (2016) - [c39]Huei-Shiuan Tang, Cheng-Yen Yang, Chih-Wei Liu, Chia-Cheng Chien:
Binaural-cue-based noise reduction using multirate quasi-ANSI filter bank for hearing aids. APCCAS 2016: 21-24 - [c38]Chi-Ming Lee, Yong-Jyun Huang, Chih-Wei Liu, Yarsun Hsu:
DeAr: A framework for power-efficient and flexible embedded digital signal processor design. APCCAS 2016: 658-661 - 2015
- [j14]Shih-Hao Ou, Kuo-Chiang Chang, Chih-Wei Liu:
An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids. Integr. 48: 230-238 (2015) - 2014
- [j13]Shin-Kai Chen, Cheng-Yu Hung, Ching-Chih Chen, Chih-Wei Liu:
Parallelizing Complex Streaming Applications on Distributed Scratchpad Memory Multicore Architecture. Int. J. Parallel Program. 42(6): 875-899 (2014) - [j12]Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu:
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 947-951 (2014) - [c37]Chia-Chen Hsu, Cheng-Yen Lin, Shin-Kai Chen, Chih-Wei Liu, Jenq Kuen Lee:
Optimized memory access support for data layout conversion on heterogeneous multi-core systems. ESTIMedia 2014: 128-137 - [c36]Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou:
An efficient 18-band quasi-ANSI 1/3-octave filter bank using re-sampling method for digital hearing aids. ICASSP 2014: 2639-2643 - [c35]Chih-Wei Liu, Le-Ren Chang-Chien
Autonomous tuning method for realizing optimal adaptive voltage positioning scheme. ISCAS 2014: 2449-2452 - [c34]Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou:
An ultra-low voltage hearing aid chip using variable-latency design technique. ISCAS 2014: 2543-2546 - [c33]Kuo-Chiang Chang, Ching-Hao Lin, Chih-Wei Liu:
Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier. VLSI-DAT 2014: 1-4 - 2013
- [j11]Chih-Wei Liu, Kuo-Chiang Chang, Ming-Hsun Chuang, Ching-Hao Lin:
10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(3): 638-649 (2013) - [j10]Shin-Kai Chen, Chih-Wei Liu, Tsung-Yi Wu, An-Chi Tsai:
Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM). IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(10): 2631-2643 (2013) - [c32]Ju-Chi Tseng, Hsin-Cheng Tseng, Chih-Wei Liu, Chia Chun Shih, Kuo-Yu Tseng, Cheng-Yu Chou, Chia-Hsuan Yu, Fang-Sun Lu:
A successful application of big data storage techniques implemented to criminal investigation for telecom. APNOMS 2013: 1-3 - [c31]Cheng-Yen Yang, Wen-Sheng Chou, Kuo-Chiang Chang, Chih-Wei Liu, Tai-Shih Chi, Shyh-Jye Jou:
Spatial-cue-based multi-band binaural noise reduction for hearing aids. SiPS 2013: 278-283 - [c30]Tsung-Ching Lin, Shin-Kai Chen, Chih-Wei Liu:
A low-error and Rom-free logarithmic arithmetic unit for embedded 3D graphics applications. VLSI-DAT 2013: 1-4 - 2012
- [c29]Cheng-Yu Chou, Chih-Wei Liu, Kuo-Yu Tseng, Chien-Wei Cheng, Fang-Sun Lu:
Challenges of system virtualization. APNOMS 2012: 1-5 - [c28]Ya-Ting Chang, Kuo-Chiang Chang, Yu-Ting Kuo, Chih-Wei Liu:
Complexity-effective auditory compensation with a controllable filter for digital hearing aids. ASP-DAC 2012: 557-558 - [c27]Shin-Kai Chen, Sheng-Yun Wu, Yu-Kai Yen, Chih-Wei Liu:
Early Stage Codesign of Multi-PE SIMD Engine: A Case Study on Object Detection. ICPP Workshops 2012: 553-560 - [c26]Shih-Hao Ou, Che-Wei Yeh, Tay-Jyi Lin, Chih-Wei Liu:
A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor. ISCAS 2012: 1335-1338 - [c25]Kuo-Chiang Chang, Yu-Wen Chen, Yu-Ting Kuo, Chih-Wei Liu:
A low power hearing aid computing platform using lightweight processing elements. ISCAS 2012: 2785-2788 - [c24]Ching-Hao Lin, Kuo-Chiang Chang, Ming-Hsun Chuang, Chih-Wei Liu:
Design and implementation of 18-band Quasi-ANSI S1.11 1/3-octave filter bank for digital hearing aids. VLSI-DAT 2012: 1-4 - 2011
- [j9]Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu:
Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters. EURASIP J. Adv. Signal Process. 2011 (2011) - 2010
- [j8]Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chih-Wei Liu:
Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1684-1696 (2010) - [c23]Meng-Ting Wang, Po-Chun Huang, Jenq Kuen Lee, Shang-Hong Lai
Support of Android lab modules for embedded system curriculum. WESE 2010: 4 - [c22]Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu:
Collaborative voltage scaling with online STA and variable-latency datapath. ACM Great Lakes Symposium on VLSI 2010: 347-352 - [c21]Kuo-Chiang Chang, Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu:
Complexity-effective dynamic range compression for digital hearing aids. ISCAS 2010: 2378-2381 - [c20]Shih-Hao Ou, Yen-Cheng Lin, Tay-Jyi Lin, Chih-Wei Liu:
Improving energy efficiency of functional units by exploiting their data-dependent latency. ISCAS 2010: 4165-4168
2000 – 2009
- 2009
- [c19]Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu:
Ultra low-power ANSI S1.11 filter bank for digital hearing aids. ASP-DAC 2009: 115-116 - [c18]Shin-Kai Chen, Tay-Jyi Lin, Chih-Wei Liu:
Parallel object detection on multicore platforms. SiPS 2009: 075-080 - 2008
- [j7]Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao:
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. J. Signal Process. Syst. 51(3): 209-223 (2008) - [c17]Shih-Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu:
Multithreaded coprocessor interface for multi-core multimedia SoC. ASP-DAC 2008: 115-116 - [c16]Yu-Ting Kuo, Tay-Jyi Lin, Wei-Han Chang, Yueh-Tai Li, Chih-Wei Liu, Shuenn-Tsong Young:
Complexity-effective auditory compensation for digital hearing aids. ISCAS 2008: 1472-1475 - [c15]Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu:
Improving datapathutilization of programmable DSP with composite functional units. ISCAS 2008: 3438-3441 - 2007
- [j6]Chih-Wei Liu, Chung-Chin Lu:
A View of Gaussian Elimination Applied to Early Stopped Berklekamp-Massey Algorithm. IEEE Trans. Commun. 55(5): 1089-1089 (2007) - [j5]Chih-Wei Liu, Chung-Chin Lu:
A View of Gaussian Elimination Applied to Early-Stopped Berlekamp-Massey Algorithm. IEEE Trans. Commun. 55(6): 1131-1143 (2007) - [j4]Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, Chih-Wei Liu:
Self-Compensation Technique for Simplified Belief-Propagation Algorithm. IEEE Trans. Signal Process. 55(6-2): 3061-3072 (2007) - [c14]Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu:
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. ASP-DAC 2007: 110-111 - [c13]Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Wei-Han Chang, Chih-Wei Liu, Shuenn-Tsong Young:
Design of ANSI S1.11 Filter Bank for Digital Hearing Aids. ICECS 2007: 242-245 - [c12]Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu:
Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. ISCAS 2007: 409-412 - [c11]Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen:
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. ISCAS 2007: 3506-3509 - 2006
- [j3]Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen:
A Compact DSP Core with Static Floating-Point Arithmetic. J. VLSI Signal Process. 42(2): 127-138 (2006) - [c10]Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen:
A 52mW 1200MIPS compact DSP for multi-core media SoC. ASP-DAC 2006: 118-119 - [c9]Cheng-Fa Tsai, Chih-Wei Liu:
KIDBSCAN: A New Efficient Data Clustering Algorithm. ICAISC 2006: 702-711 - [c8]Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen:
Programmable FIR filter with adder-based computing engine. ISCAS 2006 - [c7]Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu:
Carry Estimation for Two's Complement Fixed-Width Multipliers. SiPS 2006: 345-350 - 2005
- [c6]Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen:
A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI 2005: 50-55 - [c5]Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen:
Architecture for area-efficient 2-D transform in H.264/AVC. ICME 2005: 1126-1129 - [c4]Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen:
Pipelining technique for energy-aware datapaths. ISCAS (2) 2005: 1218-1221 - [c3]Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen:
Hierarchical instruction encoding for VLIW digital signal processors. ISCAS (4) 2005: 3503-3506 - 2004
- [c2]Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen:
A compact DSP core with static floating-point unit & its microcode generation. ACM Great Lakes Symposium on VLSI 2004: 57-60 - [c1]Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen:
Static floating-point unit with implicit exponent tracking for embedded DSP. ISCAS (2) 2004: 821-824 - 2000
- [j2]Yung-Chung Wang, Chih-Wei Liu, Chung-Chin Lu:
Loss behavior in space priority queue with batch Markovian arrival process - discrete-time case. Perform. Evaluation 41(4): 269-293 (2000)
1990 – 1999
- 1999
- [j1]Chih-Wei Liu, Kuo-Tai Huang, Chung-Chin Lu:
A Systolic Array Implementation of the Feng-Rao Algorithm. IEEE Trans. Computers 48(7): 690-706 (1999)
Coauthor Index
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last updated on 2024-09-29 01:16 CEST by the dblp team
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