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7. FPGA 1999: Monterey, CA, USA
- Sinan Kaptanoglu, Steve Trimberger:
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, CA, USA, February 21-23, 1999. ACM 1999, ISBN 1-58113-088-0 - Sinan Kaptanoglu, Greg Bakker, Arun Kundu, Ivan Corneillet, Ben Ting:
A New High Density and Very Low Cost Reprogrammable FPGA Architecture. 3-12 - Frank Heile, Andrew Leaver:
Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks. 13-16 - Om Agrawal, Herman Chang, Brad Sharpe-Geisler, Nick Schmitz, Bai Nguyen, Jack Wong, Giap Tran, Fabiano Fontana, Bill Harding:
An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-Gating Functions. 17-26 - Jason Cong, Chang Wu, Yuzheng Ding:
Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. 29-35 - Alexander Marquardt, Vaughn Betz, Jonathan Rose:
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. 37-46 - John Marty Emmert, Dinesh Bhatia:
A Methodology for Fast FPGA Floorplanning. 47-56 - Vaughn Betz, Jonathan Rose:
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. 59-68 - André DeHon:
Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization). 69-78 - S. R. Park, Wayne P. Burleson:
Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures. 81-89 - Zhiyuan Li, Scott Hauck:
Don't Care Discovery for FPGA Configuration Compression. 91-98 - Emeka Mosanya, Eduardo Sanchez:
A FPGA-Based Hardware Implementation of Generalized Profile Search Using Online Arithmetic. 101-111 - Andy Gean Ye, David M. Lewis:
Procedural Texture Mapping on FPGAs. 112-120 - William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon:
HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. 125-134 - Alan Marshall, Tony Stansfield, Igor Kostarnov, Jean Vuillemin, Brad L. Hutchings:
A Reconfigurable Arithmetic Array for Multimedia Application. 135-143 - Jeffrey A. Jacob, Paul Chow:
Memory Interfacing and Instruction Specification for Reconfigurable Processors. 145-154 - Yaska Sankar, Jonathan Rose:
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs. 157-166 - Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. 167-175 - Abdel Ejnioui, N. Ranganathan:
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. 176-185 - Huiqun Liu, D. F. Wong
:
Circuit Partitioning for Dynamically Reconfigurable FPGAs. 187-194 - Mihai Budiu, Seth Copen Goldstein:
Fast Compilation for Pipelined Reconfigurable Fabrics. 195-205 - Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi:
Configuration Caching Vs Data Caching for Striped FPGAs. 206-214 - Reetinder P. S. Sidhu, Alessandro Mei, Viktor K. Prasanna:
String Natching on Nulticontext FPGAs Using Self-Reconfiguration. 217-226 - Peter Kollig, Bashir M. Al-Hashimi:
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs. 227-234 - Karlheinz Weiß, Thorsten Steckstor, Gernot Koch, Wolfgang Rosenstiel:
Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded System. 235-242 - Bernie New, Peter Alfke:
400-MHz Frequency Counter: A Case Study in Semi-Synchronous Design. 245 - Luigi Carro:
Architecture Considerations for Mixed Signals FPGAs. 245 - Klaus Kornmesser, Torsten Kuberka, Andreas Kugel, Reinhard Männer, Stephan Rühl, M. Sessler, Holger Singpiel:
ATLANTIS - A Hybrid Approach Combining the Power of FPGA and RISC Processors Based on CompactPCI. 245 - C. Hart Poskar, Peter J. Czezowski, Robert D. McLeod:
A Computational Intelligence Based Coarse-Grained Reconfigurable Element. 246 - Hagen Ploog, Tino Rachui, Dirk Timmermann:
Design Issues in the Development of a JAVA-Processor for Small Embedded Applications. 246 - Mouna Nakkar
Dynamically Programmable Cache Evaluation and Virtualization. 246 - John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak:
Efficient Support of Hardware Debugging Through FPGA Physical Design Partitioning. 247 - Byungil Jeong, Sungjoo Yoo, Kiyoung Choi:
Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design. 247 - Herman Schmit:
Extra-Dimensional Island-Style FPGAs. 247 - A. Lecerf, François Vachon, D. Ouellet, Miguel O. Arias-Estrada:
FPGA Based Computer Vision Camera. 248 - Enrica Filippi, Archille Montanaro, Maurizio Paolini, Maura Turolla:
FPGA Design Experiences Using the CSELT VIP (TM) Library. 248 - Valery Sklyarov, José A. Fonseca, Ricardo Sal Monteiro, Arnaldo S. R. Oliveira, Andreia Melo, Nuno Lau, Konstantin Kondratjuk, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari:
FPGA-Targeted Development System for Embedded Applications. 248 - M. Anand, Sanjiv Kapoor, M. Balakrishnan:
Hardware/Software Partitioning Between Microprocessor and Reconfigurable Hardware. 249 - Lirida A. B. Naviner, Jean-Luc Danger, C. Laurent:
High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA. 249 - Chris Dick:
High-Performance 2-D FPGA DCTs Using Polynomial Transforms. 249 - John McCluskey:
High Speed Calculation of Cyclic Redundancy Codes. 250 - James Hwang, Cameron Patterson, Sujoy Mitra:
Hierarchical Placement Directives for Parametric IP Blocks. 250 - Zhijun Yang, Felipe M. G. França
Implementing an Artificial CPG Using Fine-Grain FPGAs. 250 - Akihiro Matsuura, Hidehisa Nagano, Akira Nagoya:
A Method for Implementing Fractal Image Compression on Reconfigurable Architecture. 251 - Kun-Ming Ho, Allen C.-H. Wu:
Module Generation of High Performance FPGA-Based Multipliers. 251 - Helena Krupnova, Gabriele Saucier:
Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. 251 - John McCluskey:
Practical Applications of Recursive VHDL Components in FPGA Synthesis. 252 - Philippe Soulard:
Prototyping Board and Development Environment for Rapid Prototyping of Real Time and Regular Digital Signal Processing Application. 252 - Steve Guccione, Delon Levi:
Run-Time Parameterizable Cores. 252 - Parag K. Lala, Alfred L. Burress:
Self-Checking Logic Design for LUT-Based FPGAs. 253 - Matti Tommiska:
Special Arithmetic Operations on FPGAs. 253 - Vinoo Srinivasan, Ranga Vemuri:
Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures. 253 - Florent de Dinechin, Wayne Luk, Steve McKeever:
Towards Adaptable Hierarchical Placement for FPGAs. 254 - Andreas Koch:
Unified Access to Heterogeneous Module Generators. 254 - Guang-Ming Wu, Michael Shyu, Yao-Wen Chang:
Universal Switch Blocks for Three-Dimensional FPGA Design. 254 - Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki:
Why a CAD-Verified FPGA Makes Routing so Simple and Fast! A Result of Co-Designing FPGAs and CAD Algorithms. 255 - José Luis Núñez, Claudia Feregrino, Stephen Bateman, Simon R. Jones:
The X-MatchLITE FPGA-Based Data Compressor. 255
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