default search action
Gi-Joon Nam
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [i3]Egor Zakharov, Vanessa Sklyarova, Michael Julian Black, Gi-Joon Nam, Justus Thies, Otmar Hilliges:
Human Hair Reconstruction with Strand-Aligned 3D Gaussians. CoRR abs/2409.14778 (2024) - 2023
- [c55]Chunkai Fu, Ben Trombley, Hua Xiang, Gi-Joon Nam, Jiang Hu:
Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops. ISVLSI 2023: 1-6 - [c54]Yuting Hu, Jiajie Li, Florian Klemme, Gi-Joon Nam, Tengfei Ma, Hussam Amrouch, Jinjun Xiong:
SyncTREE: Fast Timing Analysis for Integrated Circuit Design through a Physics-informed Tree-based Graph Neural Network. NeurIPS 2023 - [c53]Tingkai Liu
, Marquita Ellis
Cloud-Bursting and Autoscaling for Python-Native Scientific Workflows Using Ray. ISC Workshops 2023: 207-220 - 2022
- [j20]Rongjian Liang
Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3503-3514 (2022) - [c52]Rongjian Liang
A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions. ICCAD 2022: 64:1-64:8 - 2021
- [c51]Arjun Chaudhuri, Jonti Talukdar, Jinwook Jung, Gi-Joon Nam, Krishnendu Chakrabarty
Fault-Criticality Assessment for AI Accelerators using Graph Convolutional Networks. DATE 2021: 1596-1599 - [c50]Rongjian Liang
FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer. ICCAD 2021: 1-9 - 2020
- [c49]Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang:
Latch Clustering for Timing-Power Co-Optimization. DAC 2020: 1-6 - [c48]Hua Xiang, Gi-Joon Nam, Gustavo E. Téllez, Shyam Ramji, Xiaoqing Xu:
Self-Aligned Double-Patterning Aware Legalization. DATE 2020: 1145-1150 - [c47]Rongjian Liang
Routing-Free Crosstalk Prediction. ICCAD 2020: 163:1-163:9 - [c46]Rongjian Liang
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. ISPD 2020: 135-142 - [c45]Siyuan Chen, Jinwook Jung, Peilin Song, Krishnendu Chakrabarty
BISTLock: Efficient IP Piracy Protection using BIST. ITC 2020: 1-5 - [i2]Benjamin Tan
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR abs/2006.06806 (2020)
2010 – 2019
- 2019
- [j19]Jinwook Jung, Gi-Joon Nam, Woohyun Chung, Youngsoo Shin:
Integrated Latch Placement and Cloning for Timing Optimization. ACM Trans. Design Autom. Electr. Syst. 24(2): 22:1-22:17 (2019) - [c44]Ya-Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang, Gi-Joon Nam:
Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing. ISPD 2019: 11-18 - 2018
- [j18]Mustafa Ozdal, Gi-Joon Nam, Debbie Marr:
Guest Editors' Introduction: Hardware Accelerators for Data Centers. IEEE Des. Test 35(1): 5-6 (2018) - [j17]Jinwook Jung
OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1825-1838 (2018) - [c43]Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam:
DATC RDF: an academic flow from logic synthesis to detailed routing. ICCAD 2018: 37 - [c42]Jiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam:
Interconnect Optimization Considering Multiple Critical Paths. ISPD 2018: 132-138 - [c41]Alexey Lvov, Gustavo E. Téllez, Gi-Joon Nam:
On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques. ISPD 2018: 152-159 - [c40]Cunxi Yu
End-to-End Industrial Study of Retiming. ISVLSI 2018: 203-208 - [i1]Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam:
DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing. CoRR abs/1810.01078 (2018) - 2017
- [j16]Jinho Lee
ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator. Proc. VLDB Endow. 10(12): 1706-1717 (2017) - [c39]Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat
DATC RDF: Robust design flow database: Invited paper. ICCAD 2017: 872-873 - 2016
- [c38]Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin:
OWARU: free space-aware timing-driven incremental placement. ICCAD 2016: 8 - [c37]Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat
OpenDesign flow database: the infrastructure for VLSI design and design automation research. ICCAD 2016: 42 - 2015
- [j15]Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir A. Jamsek, Gi-Joon Nam:
Feature detection for image analytics via FPGA acceleration. IBM J. Res. Dev. 59(2/3) (2015) - [j14]Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael P. Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha:
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(10): 1537-1557 (2015) - [c36]Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins:
Toward Metrics of Design Automation Research Impact. ICCAD 2015: 263-270 - 2014
- [j13]Shantanu Dutt, Dinesh P. Mehta
New Algorithmic Techniques for Complex EDA Problems. VLSI Design 2014: 134946:1-134946:2 (2014) - [c35]Sani R. Nassif, Gi-Joon Nam, Jerry Hayes, Sani Fakhouri:
Applying VLSI EDA to energy distribution system design. ASP-DAC 2014: 91-96 - [c34]Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes:
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations. ICCAD 2014: 382-388 - [c33]Gi-Joon Nam, Sani R. Nassif:
Opportunities in power distribution network system optimization: from EDA perspective. ISPD 2014: 149-150 - 2013
- [c32]Sani R. Nassif, Gi-Joon Nam, Shayak Banerjee:
Wire delay variability in nanoscale technology and its impact on physical design. ISQED 2013: 591-596 - 2012
- [j12]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan:
An accurate sparse-matrix based framework for statistical static timing analysis. Integr. 45(4): 365-375 (2012) - [c31]Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou:
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC 2012: 465-470 - [c30]Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward:
Placement: Hot or Not? ICCAD 2012: 283-290 - 2011
- [j11]David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov:
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro 31(4): 51-62 (2011) - [c29]Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin:
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. ICCAD 2011: 640-646 - [c28]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy:
The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD 2011: 141-146 - [c27]Jeonghee Shin, John A. Darringer, Guojie Luo, Merav Aharoni, Alexey Lvov, Gi-Joon Nam, Michael B. Healy:
Floorplanning challenges in early chip planning. SoCC 2011: 388-393 - 2010
- [j10]Gi-Joon Nam, Prashant Saxena:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 169-170 (2010) - [c26]Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn:
Detecting tangled logic structures in VLSI netlists. DAC 2010: 603-608 - [c25]Taraneh Taghavi, Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Andrew D. Huber, Shyam Ramji:
New placement prediction and mitigation techniques for local routing congestion. ICCAD 2010: 621-624 - [c24]Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang
Design-hierarchy aware mixed-size placement for routability optimization. ICCAD 2010: 663-668 - [c23]Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez:
What makes a design difficult to route. ISPD 2010: 7-12 - [c22]Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu:
ITOP: integrating timing optimization within placement. ISPD 2010: 83-90
2000 – 2009
- 2009
- [c21]Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
CRISP: Congestion reduction by iterated spreading during placement. ICCAD 2009: 357-362 - [c20]Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert:
Ispd2009 clock network synthesis contest. ISPD 2009: 149-150 - [e3]Gi-Joon Nam, Prashant Saxena:
Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009. ACM 2009, ISBN 978-1-60558-449-2 [contents] - 2008
- [j9]David Z. Pan, Gi-Joon Nam:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2105-2106 (2008) - [j8]David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2156-2168 (2008) - [c19]David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD 2008: 2-9 - [c18]Gi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz:
The ISPD global routing benchmark suite. ISPD 2008: 156-159 - [e2]David Z. Pan, Gi-Joon Nam:
Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008. ACM 2008, ISBN 978-1-60558-048-7 [contents] - [r1]Gi-Joon Nam, Paul G. Villarrubia:
Placement. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j7]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
Techniques for Fast Physical Synthesis. Proc. IEEE 95(3): 573-599 (2007) - [j6]Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam:
Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2158-2172 (2007) - [c17]Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC 2007: 141-146 - [c16]Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann
Performance modeling for early analysis of multi-core systems. CODES+ISSS 2007: 209-214 - [c15]Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu:
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC 2007: 453-458 - [c14]Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden:
ISPD placement contest updates and ISPD 2007 global routing contest. ISPD 2007: 167 - [c13]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
The nuts and bolts of physical synthesis. SLIP 2007: 89-94 - [p1]Gi-Joon Nam, Charles J. Alpert, Paul G. Villarrubia:
ISPD 2005/2006 Placement Benchmarks. Modern Circuit Placement 2007: 3-12 - [e1]Gi-Joon Nam, Jason Cong:
Modern Circuit Placement, Best Practices and Results. Springer 2007, ISBN 978-0-387-36837-5 [contents] - 2006
- [j5]Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng:
A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 678-691 (2006) - [c12]Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan:
An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236 - [c11]Gi-Joon Nam:
ISPD 2006 Placement Contest: Benchmark Suite and Results. ISPD 2006: 167 - 2005
- [j4]Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake:
Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications. IEEE Trans. Very Large Scale Integr. Syst. 13(10): 1167-1178 (2005) - [c10]Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz:
Placement stability metrics. ASP-DAC 2005: 1144-1147 - [c9]Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia:
A semi-persistent clustering technique for VLSI circuit placement. ISPD 2005: 200-207 - [c8]Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz:
The ISPD2005 placement contest and benchmark suite. ISPD 2005: 216-220 - 2004
- [j3]Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. IEEE Trans. Computers 53(6): 688-696 (2004) - 2003
- [j2]Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
Effective free space management for cut-based placement via analytical constraint generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1343-1353 (2003) - 2002
- [j1]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
A new FPGA detailed routing approach via search-based Booleansatisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 674-684 (2002) - [c7]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. FPL 2002: 360-369 - [c6]Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia:
Free space management for cut-based placement. ICCAD 2002: 746-751 - 2001
- [b1]Gi-Joon Nam:
A Boolean -based layout approach and its application to FPGA routing. University of Michigan, USA, 2001 - [c5]Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake:
Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications. DAC 2001: 852-857 - [c4]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
A boolean satisfiability-based incremental rerouting approach with application to FPGAs. DATE 2001: 560-565 - [c3]Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
A comparative study of two Boolean formulations of FPGA detailed routing constraints. ISPD 2001: 222-227
1990 – 1999
- 1999
- [c2]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. FPGA 1999: 167-175 - [c1]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
Satisfiability-Based Detailed FPGA Routing. VLSI Design 1999: 574-577
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-16 21:21 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: