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NANOARCH 2016: Beijing, China
- IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016, Beijing, China, July 18-20, 2016. ACM 2016, ISBN 978-1-4503-4330-5
- He Zhang, Wang Kang, Tingting Pang, Weifeng Lv, Youguang Zhang, Weisheng Zhao:
Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM. 1-6 - Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau
, Jean-Michel Portal:
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. 7-12 - Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Sorin Cotofana
TFET NDR skewed inverter based sensing method. 13-14 - Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Inversion optimization in Majority-Inverter Graphs. 15-20 - Zhibo Wang, Rui Hua
A compare-and-select error tolerant scheme for nonvolatile processors. 21-22 - Xiaoyang Wang, Chao Zhang, Xian Zhang, Guangyu Sun:
np-ECC: Nonadjacent position error correction code for racetrack memory. 23-24 - Mingyu Li, Santosh Khasanvis, Jiajun Shi, Sachin Bhat, Mostafizur Rahman, Csaba Andras Moritz:
Towards automatic thermal network extraction in 3D ICs. 25-30 - Tian Cao, Weiqiang Liu, Chenghua Wang, Xiao-Ping Cui, Fabrizio Lombardi:
Design of approximate Redundant Binary multipliers. 31-36 - Nicoleta Cucu Laurenciu, Tushar Gupta, Valentin Savin
Error Correction Code protected Data Processing Units. 37-42 - Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels:
Synthesizing HDL to memristor technology: A generic framework. 43-48 - Peng Ouyang, Shouyi Yin, Chunxiao Xing
Energy management on DVS based coarse-grained reconfigurable platform. 49-54 - Yingyezhe Jin, Yu Liu, Peng Li:
SSO-LSM: A Sparse and Self-Organizing architecture for Liquid State Machine based neural processors. 55-60 - Sumit Dutta
Nonvolatile online CMOS trimming with magnetic tunnel junctions. 61-66 - Mahyar Shahsavari
Combining a volatile and nonvolatile memristor in artificial synapse to improve learning in Spiking Neural Networks. 67-72 - Liang Chang, Zhaohao Wang, Yuqian Gao, Wang Kang, Youguang Zhang, Weisheng Zhao:
Evaluation of spin-Hall-assisted STT-MRAM for cache replacement. 73-78 - Bo Yang, Emanuel M. Popovici, Michael Alan Quille, Andreas Amann, Sorin Cotofana
A supply voltage-dependent variation aware reliability evaluation model. 79-84 - (Withdrawn) MECRO: A local processing computer architecture based on memristor crossbar. 85-90
- (Withdrawn) Mosaic: A scheme of mapping non-volatile Boolean logic on memristor crossbar. 91-96
- Xiaoxiao Wang, Robin Tan, Marek A. Perkowski:
Synthesis of memristive circuits based on stateful IMPLY gates using an evolutionary algorithm with a correction function. 97-102 - Erya Deng, Lorena Anghel, Guillaume Prenat, Weisheng Zhao:
Multi-context non-volatile content addressable memory using magnetic tunnel junctions. 103-108 - Fengyu Qian, Yanping Gong, Guoxian Huang, Kiarash Ahi, Mehdi Anwar, Lei Wang:
A memristor-based compressive sensing architecture. 109-114 - Weiqi Zhang, Chao Zhang, Guangyu Sun:
Accelerate context switch by racetrack-SRAM hybrid cells. 115-116 - Laurie E. Calvet, Joseph S. Friedman, Damien Querlioz, Pierre Bessière, Jacques Droulez:
Sleep stage classification with stochastic Bayesian inference. 117-122 - You Wang, Hao Cai, Lirida A. B. Naviner
A novel circuit design of true random number generator using magnetic tunnel junction. 123-128 - Soroush Khaleghi, Paolo Vinella, Soumya Banerjee, Wenjing Rao
An STT-MRAM based strong PUF. 129-134 - Meshal Alawein
Improved circuit model for all-spin logic. 135-140 - Zhizhong Zhang, Yue Zhang, Lei Yue, Li Su, Yichuan Shi, Youguang Zhang, Weisheng Zhao:
Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy. 141-142 - Qian Shi, Zhaohao Wang, Yuqian Gao, Liang Chang, Wang Kang, Youguang Zhang, Weisheng Zhao:
A spin Hall effect-based multi-level cell for MRAM. 143-144 - Jiajun Shi, Mingyu Li, Santosh Khasanvis, Mostafizur Rahman, Csaba Andras Moritz:
Routability in 3D IC design: Monolithic 3D vs. Skybridge 3D CMOS. 145-150 - Naveen Kumar Macha, Md Arif Iqbal, Mostafizur Rahman:
Fine-grained 3-D CMOS concept using stacked horizontal nanowire. 151-152 - Deliang Fan:
Low power in-memory computing platform with four Terminal magnetic Domain Wall Motion devices. 153-158 - Mohammad Mahmoud A. Taha, Walt Woods, Christof Teuscher:
Approximate in-memory Hamming distance calculation with a memristive associative memory. 159-164 - Jintao Yu
Skeleton-based design and simulation flow for Computation-in-Memory architectures. 165-170 - Rotem Ben Hur, Shahar Kvatinsky:
Memory Processing Unit for in-memory processing. 171-172 - Deming Zhang, Lang Zeng, Youguang Zhang, Weisheng Zhao, Jacques-Olivier Klein
Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation. 173-178 - Leibin Ni, Hantao Huang, Hao Yu:
A memristor network with coupled oscillator and crossbar towards L2-norm based machine learning. 179-184 - Hsin-Pai Cheng, Wei Wen, Chang Song, Beiye Liu, Hai Li
Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss. 185-190 - Honglan Jiang, Cong Liu, Naman Maheshwari, Fabrizio Lombardi, Jie Han:
A comparative evaluation of approximate multipliers. 191-196 - Linbin Chen, Fabrizio Lombardi, Jie Han, Weiqiang Liu:
A fully parallel approximate CORDIC design. 197-202 - Hao Cai, You Wang, Lirida A. B. Naviner
Approximate computing in MOS/spintronic non-volatile full-adder. 203-208
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