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"A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a ..."

Hideyuki Nosaka et al. (2004)

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DOI: 10.1109/JSSC.2004.831463

access: closed

type: Journal Article

metadata version: 2023-09-30

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Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi:
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. IEEE J. Solid State Circuits 39(8): 1361-1365 (2004)

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