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Kenji Kurishima
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2010 – 2019
- 2019
- [j11]Takuya Hoshi, Norihide Kashio, Yuta Shiratori, Kenji Kurishima, Minoru Ida, Hideaki Matsuzaki:
InGaP/GaAsSb/InGaAsSb double heterojunction bipolar transistors with 703-GHz fmax and 5.4-V breakdown voltage. IEICE Electron. Express 16(3): 20181125 (2019) - 2016
- [j10]Hiroyuki Fukuyama, Michihiro Hirata, Kenji Kurishima, Minoru Ida, Masami Tokumitsu, Shogo Yamanaka, Munehiko Nagatani, Toshihiro Itoh, Kimikazu Sano, Hideyuki Nosaka, Koichi Murata:
An InP-Based 27-GHz-Bandwidth Limiting TIA IC Designed to Suppress Undershoot and Ringing in Its Output Waveform. IEICE Trans. Electron. 99-C(3): 385-396 (2016) - [j9]Norihide Kashio, Takuya Hoshi, Kenji Kurishima, Minoru Ida, Hideaki Matsuzaki:
Type-II InGaAsSb-Base Double Heterojunction Bipolar Transistors Simultaneously Exhibiting over 600-GHz fmax and 5-V Breakdown Voltage. IEICE Trans. Electron. 99-C(5): 522-527 (2016) - 2012
- [j8]Yves Bouvier, Kimikazu Sano, Munehiko Nagatani, Koichi Murata, Kenji Kurishima, Minoru Ida:
A low-power wideband InP-HBT 27-1 PRBS generator. IEICE Electron. Express 9(19): 1504-1509 (2012) - [j7]Kenji Kurishima, Minoru Ida, Norihide Kashio, Yoshino K. Fukai:
Performance of InP/InGaAs HBTs with a Thin Highly N-Type Doped Layer in the Emitter-Base Heterojunction Vicinity. IEICE Trans. Electron. 95-C(8): 1310-1316 (2012)
2000 – 2009
- 2009
- [j6]Yoshino K. Fukai, Kenji Kurishima, Norihide Kashio, Minoru Ida, Shoji Yamahata, Takatomo Enoki:
Emitter-metal-related degradation in InP-based HBTs operating at high current density and its suppression by refractory metal. Microelectron. Reliab. 49(4): 357-364 (2009) - 2008
- [j5]Norihide Kashio, Kenji Kurishima, Yoshino K. Fukai, Shoji Yamahata:
Highly Reliable Submicron InP-Based HBTs with over 300-GHz ft. IEICE Trans. Electron. 91-C(7): 1084-1090 (2008) - 2005
- [j4]Hideyuki Nosaka, Makoto Nakamura, Kimikazu Sano, Minoru Ida, Kenji Kurishima, Tsugumichi Shibata, Masami Tokumitsu, Masahiro Muraguchi:
A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation. IEICE Trans. Electron. 88-C(6): 1225-1232 (2005) - [j3]Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki:
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology. IEEE J. Solid State Circuits 40(7): 1583-1588 (2005) - 2004
- [j2]Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi:
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. IEEE J. Solid State Circuits 39(8): 1361-1365 (2004) - [c1]Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata:
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]. ESSCIRC 2004: 355-358 - 2002
- [j1]Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki:
Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors. IEEE J. Solid State Circuits 37(9): 1146-1151 (2002)
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