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Wenji Fang
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2020 – today
- 2024
- [j2]Duofa Ji, Wenji Fang, Changhai Zhai, Zelin Cao, Yuhong Ma:
TTNN: A Physically Guided Deep Learning Model for Focal Depth and Epicenter Distance Estimation Based on Multistation Waveforms. IEEE Trans. Geosci. Remote. Sens. 62: 1-11 (2024) - [c3]Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. DAC 2024: 62:1-62:6 - [i6]Mengming Li, Wenji Fang, Qijun Zhang, Zhiyao Xie:
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model. CoRR abs/2401.13266 (2024) - [i5]Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, Zhiyao Xie:
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR abs/2402.00386 (2024) - [i4]Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou:
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR abs/2403.07257 (2024) - [i3]Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. CoRR abs/2403.18453 (2024) - 2023
- [j1]Wenji Fang, Guangyu Hu, Hongce Zhang:
r-map: Relating Implementation and Specification in Hardware Refinement Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 5113-5126 (2023) - [c2]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. ICCAD 2023: 1-9 - [c1]Wenji Fang, Hongce Zhang:
WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification. TACAS (2) 2023: 11-18 - [i2]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. CoRR abs/2311.08441 (2023) - [i1]Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie:
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. CoRR abs/2312.08617 (2023)
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last updated on 2024-12-02 21:27 CET by the dblp team
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