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"Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing ..."

Wenji Fang et al. (2024)

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DOI: 10.1145/3649329.3655671

access: closed

type: Conference or Workshop Paper

metadata version: 2024-11-30

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  dblp key:
  - conf/dac/FangLZX24
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  - https://dblp.org/rec/conf/dac/FangLZX24
Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. DAC 2024: 62:1-62:6

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