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Gyungock Kim
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2010 – 2019
- 2018
- [j6]Jeongho Hwang
, Gyu-Seob Jeong, Woo-Rham Bae
A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(4): 436-440 (2018) - [j5]Gyu-Seob Jeong
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1395-1399 (2018) - [j4]Hong-Seok Choi, Jeongho Hwang
A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1824-1828 (2018) - 2016
- [j3]Yoonsoo Kim, Gyu-Seob Jeong, Jun-Eun Park
20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1034-1038 (2016) - 2015
- [j2]Sang-Hyeok Chu, Woo-Rham Bae
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. IEEE J. Solid State Circuits 50(11): 2603-2612 (2015) - [c4]Sungwoo Kim, Sungchun Jang, Jun-Eun Park
A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop. ISCAS 2015: 2856-2859 - [c3]Jun-Eun Park
20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS. ISCAS 2015: 2864-2867 - 2014
- [c2]Sang-Hyeok Chu, Woo-Rham Bae
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. A-SSCC 2014: 101-104 - 2013
- [c1]Dong-Wook Kim, Hankyu Chi, Yu-Sang Chun, Myung-Heon Chin, Gyungock Kim, Deog-Kyoon Jeong:
12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS. ISCAS 2013: 1115-1118
2000 – 2009
- 2008
- [j1]A-Ram Choi, Sang-Sik Choi, Byung-Guan Park, Dongwoo Suh, Gyungock Kim, Jin-Tae Kim, Jin-Soo Choi, Deok Ho Cho, Tae-Hyun Han, Kyu-Hwan Shim:
Selective Epitaxial Growth of SiGe Layers with High Aspect Ratio Mask of Dielectric Films. IEICE Trans. Electron. 91-C(5): 767-771 (2008)
Coauthor Index
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