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Vojtech Mrazek
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2020 – today
- 2024
- [j15]Jirí Síma, Petra Vidnerová, Vojtech Mrazek:
Energy Complexity of Convolutional Neural Networks. Neural Comput. 36(8): 1601-1625 (2024) - [c45]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. DATE 2024: 1-6 - [c44]Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. DDECS 2024: 1-6 - [c43]Michal Pinos, Lukás Sekanina, Vojtech Mrazek:
ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. IJCNN 2024: 1-8 - [i20]Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. CoRR abs/2404.05368 (2024) - [i19]Michal Pinos, Lukás Sekanina, Vojtech Mrazek:
ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. CoRR abs/2404.08002 (2024) - [i18]Vojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vasícek, Kostas Siozios, Georgios Tzimpragos, Mehdi Baradaran Tahoori, Georgios Zervakis:
Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. CoRR abs/2407.20589 (2024) - 2023
- [j14]Michal Pinos, Vojtech Mrazek
, Filip Vaverka, Zdenek Vasícek
Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 212-224 (2023) - [c42]Martin Hurta
ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DATE 2023: 1-2 - [c41]Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. DDECS 2023: 45-50 - [c40]Vojtech Mrazek
Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial). DDECS 2023: 91-92 - [c39]Martin Hurta
MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. DDECS 2023: 155-160 - [c38]Vojtech Mrazek
Effective EEG Feature Selection for Interpretable MDD (Major Depressive Disorder) Classification. GECCO 2023: 1427-1435 - [c37]Jirí Síma, Petra Vidnerová
Energy Complexity Model for Convolutional Neural Networks. ICANN (10) 2023: 186-198 - [c36]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique
Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. ICCAD 2023: 1-9 - [i17]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. CoRR abs/2303.04734 (2023) - 2022
- [j13]Alberto Marchisio
RoHNAS: A Neural Architecture Search Framework With Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. IEEE Access 10: 109043-109055 (2022) - [j12]Michal Pinos, Vojtech Mrazek
Evolutionary approximation and neural architecture search. Genet. Program. Evolvable Mach. 23(3): 351-374 (2022) - [j11]Milan Ceska
SagTree: Towards efficient mutation in evolutionary circuit approximation. Swarm Evol. Comput. 69: 100986 (2022) - [c35]Jan Klhufek
ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. DDECS 2022: 44-47 - [c34]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Tomás Vojnar:
Designing Approximate Arithmetic Circuits with Combined Error Constraints. DSD 2022: 785-792 - [c33]Vojtech Mrazek:
Optimization of BDD-based Approximation Error Metrics Calculations. ISVLSI 2022: 86-91 - [c32]Martin Hurta
Evolutionary Design of Reduced Precision Preprocessor for Levodopa-Induced Dyskinesia Classifier. PPSN (1) 2022: 491-504 - [i16]Jan Klhufek, Vojtech Mrazek:
ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. CoRR abs/2203.04649 (2022) - [i15]Vojtech Mrazek:
Optimization of BDD-based Approximation Error Metrics Calculations. CoRR abs/2205.03267 (2022) - [i14]Milan Ceska
Designing Approximate Arithmetic Circuits with Combined Error Constraints. CoRR abs/2206.13077 (2022) - [i13]Alberto Marchisio, Vojtech Mrazek, Andrea Massa, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique:
RoHNAS: A Neural Architecture Search Framework with Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. CoRR abs/2210.05276 (2022) - 2021
- [j10]David Hodan, Vojtech Mrazek, Zdenek Vasícek
Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genet. Program. Evolvable Mach. 22(4): 539-572 (2021) - [j9]Alberto Marchisio
DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1768-1781 (2021) - [j8]Alberto Marchisio
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 716-729 (2021) - [c31]Michal Pinos, Vojtech Mrazek
Evolutionary Neural Architecture Search Supporting Approximate Multipliers. EuroGP 2021: 82-97 - [e1]Muhammad Shafique, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek:
24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021. IEEE 2021, ISBN 978-1-6654-3595-6 [contents] - [i12]Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
Evolutionary Neural Architecture Search Supporting Approximate Multipliers. CoRR abs/2101.11883 (2021) - 2020
- [j7]Milan Ceska
Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Appl. Soft Comput. 95: 106466 (2020) - [j6]Vojtech Mrazek
Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(4): 406-418 (2020) - [j5]Mohammad Saeed Ansari
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 317-328 (2020) - [c30]Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek:
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. AICAS 2020: 243-247 - [c29]Alessio Colucci, Alberto Marchisio
A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. CODES+ISSS 2020: 34-36 - [c28]Bharath Srinivas Prabakaran, Vojtech Mrazek
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. DAC 2020: 1-6 - [c27]Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. DATE 2020: 294-297 - [c26]Alberto Marchisio
ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. DATE 2020: 1205-1210 - [c25]David Hodan, Vojtech Mrazek
Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. GECCO 2020: 940-948 - [c24]Alberto Marchisio
NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. ICCAD 2020: 114:1-114:9 - [c23]Milan Ceska
Satisfiability Solving Meets Evolutionary Optimisation in Designing Approximate Circuits. SAT 2020: 481-491 - [i11]Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. CoRR abs/2002.09481 (2020) - [i10]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
Adaptive Verifiability-Driven Strategy for Evolutionary Approximation of Arithmetic Circuits. CoRR abs/2003.02491 (2020) - [i9]Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek:
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. CoRR abs/2004.10483 (2020) - [i8]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. CoRR abs/2004.10502 (2020) - [i7]David Hodan, Vojtech Mrazek, Zdenek Vasícek:
Semantically-Oriented Mutation Operator in Cartesian Genetic Programming for Evolutionary Circuit Design. CoRR abs/2004.11018 (2020) - [i6]Alberto Marchisio, Andrea Massa, Vojtech Mrazek, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique:
NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. CoRR abs/2008.08476 (2020) - [i5]Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique:
DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. CoRR abs/2010.05754 (2020)
2010 – 2019
- 2019
- [j4]Vojtech Mrazek
Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2734-2744 (2019) - [c22]Vojtech Mrazek
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. DAC 2019: 123 - [c21]Zdenek Vasícek, Vojtech Mrazek
Automated Circuit Approximation Method Driven by Data Distribution. DATE 2019: 96-101 - [c20]Vojtech Mrazek
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. ICCAD 2019: 1-8 - [p1]Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek:
Automated Search-Based Functional Approximation for Digital Circuits. Approximate Circuits 2019: 175-203 - [i4]Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. CoRR abs/1902.10807 (2019) - [i3]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Automated Circuit Approximation Method Driven by Data Distribution. CoRR abs/1903.04188 (2019) - [i2]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique:
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. CoRR abs/1907.07229 (2019) - [i1]Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique:
ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. CoRR abs/1912.00700 (2019) - 2018
- [j3]Vojtech Mrazek
Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Comput. Digit. Tech. 12(4): 139-149 (2018) - [j2]Vojtech Mrazek
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2572-2576 (2018) - [c19]Vojtech Mrazek
Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. AHS 2018: 264-271 - [c18]Milan Ceska
ADAC: Automated Design of Approximate Circuits. CAV (1) 2018: 612-620 - [c17]Vojtech Mrazek
Evolutionary design of large approximate adders optimized for various error criteria. GECCO (Companion) 2018: 294-295 - [c16]Vojtech Mrazek
Evolving boolean functions for fast and efficient randomness testing. GECCO 2018: 1302-1309 - [c15]Lukás Sekanina, Vojtech Mrazek
Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. ICECS 2018: 377-380 - 2017
- [j1]Zdenek Vasícek, Vojtech Mrazek
Trading between quality and non-functional properties of median filter in embedded systems. Genet. Program. Evolvable Mach. 18(1): 45-82 (2017) - [c14]Vojtech Mrazek
EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. DATE 2017: 258-261 - [c13]Zdenek Vasícek, Vojtech Mrazek
Towards low power approximate DCT architecture for HEVC standard. DATE 2017: 1576-1581 - [c12]Vojtech Mrazek
Parallel optimization of transistor level circuits using cartesian genetic programming. GECCO (Companion) 2017: 1849-1856 - [c11]Milan Ceska
Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. ICCAD 2017: 416-423 - [c10]Muhammad Shafique
Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. ISVLSI 2017: 627-632 - 2016
- [c9]Radek Hrbacek, Vojtech Mrazek
Automatic design of approximate circuits by means of multi-objective evolutionary algorithms. DTIS 2016: 1-6 - [c8]Vojtech Mrazek
Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD 2016: 81 - [c7]Vojtech Mrazek
Automatic design of arbitrary-size approximate sorting networks with error guarantee. PATMOS 2016: 221-228 - [c6]Jan Nevoral
Evolutionary design of polymorphic gates using ambipolar transistors. SSCI 2016: 1-8 - [c5]Zdenek Vasícek, Vojtech Mrazek
Evolutionary functional approximation of circuits implemented into FPGAs. SSCI 2016: 1-8 - 2015
- [c4]Vojtech Mrazek
Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. EUC 2015: 106-113 - [c3]Vojtech Mrazek
Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. EuroGP 2015: 66-77 - [c2]Vojtech Mrazek
Evolutionary Approximation of Software for Embedded Systems: Median Function. GECCO (Companion) 2015: 795-801 - 2014
- [c1]Vojtech Mrazek
Acceleration of transistor-level evolution using Xilinx Zynq Platform. ICES 2014: 9-16
Coauthor Index
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last updated on 2024-11-27 20:26 CET by the dblp team
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