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"Automated Verifiability-Driven Design of Approximate Circuits: Exploiting ..."

Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina (2024)

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DOI: 10.23919/DATE58400.2024.10546795

access: closed

type: Conference or Workshop Paper

metadata version: 2024-09-30

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Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. DATE 2024: 1-6

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