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Robert K. Montoye
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2020 – today
- 2021
- [c21]Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam
, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose:
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA 2021: 29-42
2010 – 2019
- 2017
- [c20]Ramon Bertran
Very Low Voltage (VLV) Design. ICCD 2017: 601-604 - 2014
- [j10]Jing Li
1 Mb 0.41 µm2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing. IEEE J. Solid State Circuits 49(4): 896-907 (2014) - [c19]Dheeraj Sreedhar, Jeff H. Derby, Robert K. Montoye, Charles L. Johnson:
Matrix-matrix multiplication on a large register file architecture with indirection. HiPC 2014: 1-10 - 2013
- [c18]Dheeraj Sreedhar, Jeff H. Derby, Augusto J. Vega, Brian Rogers, Charles L. Johnson, Robert K. Montoye:
Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure. ICASSP 2013: 2770-2774 - [c17]Yong Liu, Ping-Hsuan Hsieh
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. ISSCC 2013: 400-401 - 2012
- [c16]Augusto Vega, Pradip Bose, Alper Buyuktosunoglu, Jeff H. Derby, Michele Franceschini, Charles Johnson, Robert K. Montoye:
Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor. HPCA 2012: 423-432 - 2011
- [c15]Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. CICC 2011: 1-4 - [c14]Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter F. Wendel, Leland Chang:
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. ISSCC 2011: 256-258 - 2010
- [j9]Leland Chang, David J. Frank, Robert K. Montoye, Steven J. Koester
Practical Strategies for Power-Efficient Computing Technologies. Proc. IEEE 98(2): 215-236 (2010) - [j8]Xiao Yan Zhang, Yiu-Hing Chan, Robert K. Montoye, Leon J. Sigal, Eric M. Schwarz, Michael Kelly:
A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit. J. Signal Process. Syst. 58(2): 139-144 (2010) - [c13]Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose:
Performance and power evaluation of an in-line accelerator. Conf. Computing Frontiers 2010: 81-82
2000 – 2009
- 2008
- [j7]Leland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek:
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches. IEEE J. Solid State Circuits 43(4): 956-963 (2008) - [c12]Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye:
Custom is from Venus and synthesis from Mars. DAC 2008: 992 - 2006
- [j6]Wendy Belluomini, Damir Jamsek, Andrew K. Martin, Chandler McDowell, Robert K. Montoye, Hung C. Ngo, Jun Sawada:
Limited switch dynamic logic circuits for high-speed low-power circuit design. IBM J. Res. Dev. 50(2-3): 277-286 (2006) - [c11]Jeff H. Derby, Robert K. Montoye, José E. Moreira:
VICTORIA: VMX indirect compute technology oriented towards in-line acceleration. Conf. Computing Frontiers 2006: 303-312 - [c10]Xiao Yan Yu, Robert K. Montoye, Kevin J. Nowka
Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. PATMOS 2006: 47-55 - [c9]Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown:
Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems. VLSI Design 2006: 89-93 - 2005
- [c8]Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka
Controlled-Load Limited Switch Dynamic Logic Circuit. ISQED 2005: 83-87 - [c7]Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham:
Testing and debugging delay faults in dynamic circuits. ITC 2005: 10 - 2004
- [c6]Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka:
A low latency and low power dynamic Carry Save Adder. ISCAS (2) 2004: 477-480 - [c5]Robert K. Montoye:
The four degrees of 3D. ISPD 2004: 1 - [c4]Robert K. Montoye:
The four degrees of 3D. ISPD 2004: 107
1990 – 1999
- 1998
- [j5]Timothy M. Kemp, Robert K. Montoye, Jeffrey D. Harper, John D. Palmer, Daniel J. Auerbach:
A decompression core for PowerPC. IBM J. Res. Dev. 42(6): 807-812 (1998) - 1990
- [j4]H. B. Bakoglu, Gregory F. Grohoski, Robert K. Montoye:
The IBM RISC System/6000 Processor: Hardware Overview. IBM J. Res. Dev. 34(1): 12-22 (1990) - [j3]Robert K. Montoye, Erdem Hokenek, Stephen L. Runyon:
Design of the IBM RISC System/6000 Floating-Point Execution Unit. IBM J. Res. Dev. 34(1): 59-70 (1990) - [j2]Erdem Hokenek, Robert K. Montoye:
Leading-Zero Anticipator (LZA) in the IBM RISC System/6000 Floating-Point Execution Unit. IBM J. Res. Dev. 34(1): 71-77 (1990) - [c3]H. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan:
IBM second-generation RISC machine organization. Compcon 1990: 173-178
1980 – 1989
- 1989
- [c2]H. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan:
IBM second-generation RISC machine organization. ICCD 1989: 138-142 - 1984
- [b1]Robert K. Montoye:
Optimization and Testing of Nmos Arithmetic Structures (Vlsi, Mos). University of Illinois Urbana-Champaign, USA, 1984 - 1982
- [j1]Robert K. Montoye, Duncan H. Lawrie:
A Practical Algorithm for the Solution of Triangular Systems on a Parallel Processing System. IEEE Trans. Computers 31(11): 1076-1082 (1982) - 1981
- [c1]Robert K. Montoye:
Area-time efficient addition in charge based technology. DAC 1981: 862-872
Coauthor Index
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