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Syed M. Alam
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2020 – today
- 2023
- [j12]Zachary Kahleifeh, Himanshu Thapliyal
, Syed M. Alam:
Adiabatic/MTJ-Based Physically Unclonable Function for Consumer Electronics Security. IEEE Trans. Consumer Electron. 69(1): 1-8 (2023) - 2022
- [c17]Syed M. Alam, Dimitri Houssameddine, F. Neumeyer, I. Rahman, M. DeHerrera, S. Ikegawa, P. Sanchez, X. Zhang, Y. Wang, J. Williams, Dietmar Gogl, H. Xu, M. Farook, D. Aceves, H. K. Lee, Fred B. Mancoff, M. Chou, CH. Tan, B. Huang, S. Mukherjee, M. Lu, A. Shah, K. Nagel, Y. Kim, S. Aggarwal:
Persistent xSPI STT-MRAM with up to 400MB/s Read and Write Throughput. IMW 2022: 1-4 - 2021
- [c16]J. J. Sun, M. DeHerrera, B. Hughes, S. Ikegawa, H. K. Lee, Fred B. Mancoff, K. Nagel, G. Shimon, Syed M. Alam, D. Houssameddine, S. Aggarwal:
Commercialization of 1Gb Standalone Spin-Transfer Torque MRAM. IMW 2021: 1-4
2010 – 2019
- 2014
- [j11]Jayita Das, Syed M. Alam, Sanjukta Bhanja:
Nano Magnetic STT-Logic Partitioning for Optimum Performance. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 90-98 (2014) - [p1]Jayita Das, Syed M. Alam, Sanjukta Bhanja:
STT-Based Non-Volatile Logic-in-Memory Framework. Field-Coupled Nanocomputing 2014: 173-193 - 2013
- [c15]Thomas W. Andre, Syed M. Alam, Dietmar Gogl, C. K. Subramanian, Hal Lin, W. Meadows, X. Zhang, Nicholas D. Rizzo, Jason Janesky, D. Houssameddine, Jon M. Slaughter:
ST-MRAM fundamentals, challenges, and applications. CICC 2013: 1-8 - [c14]Mark M. Budnik, Rasit Onur Topaloglu
Welcome to ISQED 2013. ISQED 2013 - 2012
- [j10]Jayita Das, Syed M. Alam, Sanjukta Bhanja:
Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 2008-2016 (2012) - [c13]Jayita Das, Syed M. Alam, Sanjukta Bhanja:
Non-destructive variability tolerant differential read for non-volatile logic. MWSCAS 2012: 178-181 - 2011
- [j9]Jayita Das, Syed M. Alam, Sanjukta Bhanja:
Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 267-276 (2011) - [j8]Ankur Jain, Syed M. Alam, Scott Pozder, Robert E. Jones:
Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints. IET Comput. Digit. Tech. 5(3): 169-178 (2011) - [j7]Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja:
Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis. Microelectron. Reliab. 51(2): 485-501 (2011) - [j6]Nauman H. Khan, Syed M. Alam, Soha Hassoun:
Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 647-658 (2011) - [c12]Nauman H. Khan, Syed M. Alam, Soha Hassoun:
Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs. ISQED 2011: 751-756 - 2010
- [j5]Alodeep Sanyal, Syed M. Alam, Sandip Kundu:
BIST to Detect and Characterize Transient and Parametric Failures. IEEE Des. Test Comput. 27(5): 50-59 (2010) - [j4]Ioannis Savidis, Syed M. Alam, Ankur Jain, Scott Pozder, Robert E. Jones, Ritwik Chatterjee:
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. Microelectron. J. 41(1): 9-16 (2010) - [j3]Syed M. Alam, Robert E. Jones, Scott Pozder, Ritwik Chatterjee, Shahid Rauf, Ankur Jain:
Interstratum Connection Design Considerations for Cost-Effective 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 450-460 (2010)
2000 – 2009
- 2009
- [c11]Nauman H. Khan, Syed M. Alam, Soha Hassoun:
Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. 3DIC 2009: 1-7 - [c10]Nauman H. Khan, Syed M. Alam, Soha Hassoun:
System-level comparison of power delivery design for 2D and 3D ICs. 3DIC 2009: 1-7 - [c9]Syed M. Alam, Robert E. Jones, Scott Pozder, Ankur Jain:
Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology. ISQED 2009: 569-575 - [i1]Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja:
Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis. CoRR abs/0906.3282 (2009) - 2008
- [j2]Joseph J. Nahas, Thomas W. Andre, Brad Garni, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino:
A 180 Kbit Embeddable MRAM Memory Module. IEEE J. Solid State Circuits 43(8): 1826-1834 (2008) - [c8]Syed M. Alam, Mike Ignatowski, Yuan Xie:
Technology, CAD tools, and designs for emerging 3D integration technology. ACM Great Lakes Symposium on VLSI 2008: 1-2 - [c7]Alodeep Sanyal, Syed M. Alam, Sandip Kundu:
A Built-In Self-Test Scheme for Soft Error Rate Characterization. IOLTS 2008: 65-70 - 2007
- [j1]Syed M. Alam, Chee Lip Gan
Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations. Microelectron. J. 38(4-5): 463-473 (2007) - [c6]Joseph J. Nahas, Thomas W. Andre, Chitra K. Subramanian, Hal Lin, Syed M. Alam, Ken Papworth, William L. Martino:
A 180 Kbit Embeddable MRAM Memory Module. CICC 2007: 791-794 - [c5]Syed M. Alam, Robert E. Jones, Shahid Rauf, Ritwik Chatterjee:
Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology. ISQED 2007: 580-585 - 2005
- [c4]Syed M. Alam, Donald E. Troxel, Carl V. Thompson:
Thermal aware cell-based full-chip electromigration reliability analysis. ACM Great Lakes Symposium on VLSI 2005: 26-31 - [c3]Syed M. Alam, Frank L. Wei, Chee Lip Gan
Electromigration Reliability Comparison of Cu and Al Interconnects. ISQED 2005: 303-308 - 2004
- [b1]Syed M. Alam:
Design tool and methodologies for interconnect reliability analysis in integrated circuits. Massachusetts Institute of Technology, Cambridge, MA, USA, 2004 - [c2]Syed M. Alam, Chee Lip Gan
Circuit Level Reliability Analysis of Cu Interconnects. ISQED 2004: 238-243 - 2002
- [c1]Syed M. Alam, Donald E. Troxel, Carl V. Thompson:
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits. ISQED 2002: 246-251
Coauthor Index
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