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2020 – today

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2024
[j11]
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Lorién López-Villellas, Rubén Langarita-Benítez, Asaf Badouh, Víctor Soria Pardos, Quim Aguado-Puig, Guillem López-Paradís, Max Doblas, Javier Setoain, Chulho Kim, Makoto Ono, Adrià Armejach, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó:
GenArchBench: A genomics benchmark suite for arm HPC processors. Future Gener. Comput. Syst. 157: 313-329 (2024)
[j10]
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Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó:
SpChar: Characterizing the sparse puzzle via decision trees. J. Parallel Distributed Comput. 192: 104941 (2024)
[c28]
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Francesc Martínez Palau, Martí Torrents, Adrià Armejach, Marc Casas:
Exploiting Vector Code Semantics for Efficient Data Cache Prefetching. ICS 2024: 98-109
[c27]
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Pouya Esmaili-Dokht, Francesco Sgherzi, Valéria Soldera Girelli, Isaac Boixaderas, Mariana Carmin, Alireza Monemi, Adrià Armejach, Estanislao Mercadal, Germán Llort, Petar Radojkovic, Miquel Moretó, Judit Giménez, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Emanuele Confalonieri, Rishabh Dubey, Jason Adlard:
A Mess of Memory System Benchmarking, Simulation and Application Profiling. MICRO 2024: 136-152
[i3]
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  - journals/corr/abs-2405-10170
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Pouya Esmaili-Dokht, Francesco Sgherzi, Valéria Soldera Girelli, Isaac Boixaderas, Mariana Carmin, Alireza Momeni, Adrià Armejach, Estanislao Mercadal, Germán Llort, Petar Radojkovic, Miquel Moretó, Judit Giménez, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Emanuele Confalonieri, Rishabh Dubey, Jason Adlard:
A Mess of Memory System Benchmarking, Simulation and Application Profiling. CoRR abs/2405.10170 (2024)
2023
[j9]
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Rubén Langarita, Adrià Armejach, Pablo Ibáñez, Jesús Alastruey-Benedé, Miquel Moretó:
Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor. IEEE ACM Trans. Comput. Biol. Bioinform. 20(5): 3139-3153 (2023)
[c26]
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Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó, Jonathan Balkind:
Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi. DATE 2023: 1-6
[c25]
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Víctor Soria Pardos, Adrià Armejach, Tiago Mück, Darío Suárez Gracia, José A. Joao, Alejandro Rico, Miquel Moretó:
DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations. ISCA 2023: 30:1-30:13
[c24]
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Marco Siracusa, Víctor Soria Pardos, Francesco Sgherzi, Joshua Randall, Douglas J. Joseph, Miquel Moretó Planas, Adrià Armejach:
A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors. MICRO 2023: 1332-1346
[c23]
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Alexandre de Limas Santana, Adrià Armejach, Marc Casas:
Efficient Direct Convolution Using Long SIMD Instructions. PPoPP 2023: 342-353
[c22]
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Guillem López-Paradís, Balaji Venu, Adrià Armejach, Miquel Moretó:
Characterization of a Coherent Hardware Accelerator Framework for SoCs. SAMOS 2023: 91-106
[i2]
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  - journals/corr/abs-2304-06944
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Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó:
SpChar: Characterizing the Sparse Puzzle via Decision Trees. CoRR abs/2304.06944 (2023)
2022
[j8]
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  - journals/tcbb/LangaritaASIAM22
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Rubén Langarita, Adrià Armejach, Javier Setoain, Pablo Ibáñez-Marín, Jesús Alastruey-Benedé, Miquel Moretó:
Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps. IEEE ACM Trans. Comput. Biol. Bioinform. 19(1): 355-368 (2022)
[j7]
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  - journals/tetc/RiosAPHC22
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John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas:
A BF16 FMA is All You Need for DNN Training. IEEE Trans. Emerg. Top. Comput. 10(3): 1302-1314 (2022)
[c21]
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John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas:
A BF16 FMA is All You Need for DNN Training. ARITH 2022: 9
[c20]
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John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas:
FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats. ISPASS 2022: 144-146
[c19]
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John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas:
FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats. ECML/PKDD (5) 2022: 480-497
2021
[j6]
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Víctor Soria Pardos, Adrià Armejach, Darío Suárez Gracia, Miquel Moretó:
On the use of many-core Marvell ThunderX2 processor for HPC workloads. J. Supercomput. 77(4): 3315-3338 (2021)
[c18]
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Adrià Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem López-Paradís, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji:
Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors. DATE 2021: 136-141
[c17]
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John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas:
Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training. ICMLA 2021: 980-987
[c16]
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Guillem López-Paradís, Adrià Armejach, Miquel Moretó:
gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator. ICPP 2021: 29:1-29:11
[c15]
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  - conf/ics/BarredoABM21
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Adrián Barredo, Adrià Armejach, Jonathan C. Beard, Miquel Moretó:
PLANAR: a programmable accelerator for near-memory data rearrangement. ICS 2021: 164-176
[c14]
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  - conf/pmbs-ws/ZaourarBMJSWFHP21
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Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau:
Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS 2021: 18-29
2020
[j5]
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Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó:
Using Arm's scalable vector extension on stencil codes. J. Supercomput. 76(3): 2039-2062 (2020)
[c13]
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  - conf/icmla/RiosAKPVC20
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John Osorio Ríos, Adrià Armejach, Gulrukh Khattak, Eric Petit, Sofia Vallecorsa, Marc Casas:
Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors. ICMLA 2020: 49-56
[i1]
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  - journals/corr/abs-2007-03152
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Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian:
The gem5 Simulator: Version 20.0+. CoRR abs/2007.03152 (2020)

2010 – 2019

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2019
[j4]
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Adrià Armejach, Marc Casas, Miquel Moretó:
Design trade-offs for emerging HPC processors based on mobile market technology. J. Supercomput. 75(9): 5717-5740 (2019)
[c12]
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  - conf/ipps/GomezMAMMC19
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Constantino Gómez, Francesc Martínez, Adrià Armejach, Miquel Moretó, Filippo Mantovani, Marc Casas:
Design Space Exploration of Next-Generation HPC Machines. IPDPS 2019: 54-65
2018
[c11]
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Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó:
Stencil codes on a vector length agnostic architecture. PACT 2018: 13:1-13:12
2016
[j3]
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Oriol Arcas-Abella, Adrià Armejach, Timothy Hayes, Gorker Alp Malazgirt, Oscar Palomar, Behzad Salami, Nehir Sönmez:
Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory. Comput. Sci. Eng. 18(1): 80-87 (2016)
[c10]
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Naveed Ul Mustafa, Adrià Armejach, Özcan Özturk, Adrián Cristal, Osman S. Unsal:
Implications of non-volatile memory as primary storage for database management systems. SAMOS 2016: 164-171
[c9]
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Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, Miquel Moretó:
MUSA: a multi-level simulation approach for next-generation HPC machines. SC 2016: 526-537
2015
[c8]
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Adrià Armejach, Adrián Cristal, Osman S. Unsal:
Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches. SBAC-PAD 2015: 65-73
2014
[b1]
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Adrià Armejach:
Techniques to improve concurrency in hardware transactional memory. Polytechnic University of Catalonia, Spain, 2014
[c7]
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Oriol Arcas-Abella, Geoffrey Ndu, Nehir Sönmez, Mohsen Ghasempour, Adrià Armejach, Javier Navaridas, Wei Song, John Mawer, Adrián Cristal, Mikel Luján:
An empirical evaluation of High-Level Synthesis languages and tools for database acceleration. FPL 2014: 1-8
2013
[j2]
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  - journals/taco/ArmejachGNUC13
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Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal:
Techniques to improve performance in requester-wins hardware transactional memory. ACM Trans. Archit. Code Optim. 10(4): 42:1-42:25 (2013)
[c6]
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Adrià Armejach, Anurag Negi, Adrián Cristal, Osman S. Unsal, Per Stenström, Tim Harris:
HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. HiPC 2013: 196-205
2012
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Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache. Integr. 45(3): 237-245 (2012)
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  - conf/IEEEpact/NegiACUS12
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Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström:
Transactional prefetching: narrowing the window of contention in hardware transactional memory. PACT 2012: 181-190
[c4]
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  - conf/norchip/SeyediACUV12
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Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Novel SRAM bias control circuits for a low power L1 data cache. NORCHIP 2012: 1-6
2011
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Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. PACT 2011: 361-371
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Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache for optimistic concurrency. ACM Great Lakes Symposium on VLSI 2011: 325-330

2000 – 2009

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2009
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Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero:
EazyHTM: eager-lazy hardware transactional memory. MICRO 2009: 145-155

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