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Oriol Arcas-Abella
Person information
- affiliation: Barcelona Supercomputing Center (BSC), Barcelona, Spain
- affiliation: Polytechnic University of Catalonia (UPC), Barcelona, Spain
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2020 – today
- 2020
- [c10]Francesco Ciaccia, Ivan Romero, Oriol Arcas-Abella, Diego Montero, René Serral-Gracià, Mario Nemirovsky:
SABES: Statistical Available Bandwidth EStimation from passive TCP measurements. Networking 2020: 743-748 - [i1]Oriol Arcas-Abella
, Abhinav Agarwal:
Architectural Analysis of FPGA Technology Impact. CoRR abs/2008.13430 (2020)
2010 – 2019
- 2019
- [c9]Francesco Ciaccia, Oriol Arcas-Abella
Improving TCP Performance and Reducing Self-Induced Congestion with Receive Window Modulation. ICCCN 2019: 1-6 - 2017
- [j3]Behzad Salami
AxleDB: A novel programmable query processing platform on FPGA. Microprocess. Microsystems 51: 142-164 (2017) - 2016
- [b1]Oriol Arcas-Abella:
Multicore architecture prototyping on reconfigurable devices. Polytechnic University of Catalonia, Spain, 2016 - [j2]Oriol Arcas-Abella
Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory. Comput. Sci. Eng. 18(1): 80-87 (2016) - [c8]Behzad Salami
Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique. CARLA 2016: 131-145 - [p1]Oriol Arcas-Abella
Bluespec SystemVerilog. FPGAs for Software Programmers 2016: 165-172 - 2015
- [c7]Oriol Arcas-Abella
High-Level Debugging and Verification for FPGA-Based Multicore Architectures. FCCM 2015: 135-142 - [c6]Behzad Salami
HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA. FCCM 2015: 163 - 2014
- [c5]Oriol Arcas-Abella
An empirical evaluation of High-Level Synthesis languages and tools for database acceleration. FPL 2014: 1-8 - 2013
- [c4]Myron King, Asif Khan, Abhinav Agarwal, Oriol Arcas
Generating infrastructure for FPGA-accelerated applications. FPL 2013: 1-6 - 2012
- [j1]Oriol Arcas
Resource-bounded multicore emulation using Beefarm. Microprocess. Microsystems 36(8): 620-631 (2012) - [c3]Oriol Arcas
A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory. FCCM 2012: 1-8 - 2011
- [c2]Nehir Sönmez
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype. ARC 2011: 350-362 - [c1]Nehir Sönmez
TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. FCCM 2011: 146-153
Coauthor Index
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last updated on 2024-04-25 05:58 CEST by the dblp team
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