default search action
IET Computers & Digital Techniques, Volume 12
Volume 12, Number 1, January 2018
- Amir Fadakar Noghondar, Midia Reshadi, Nader Bagherzadeh
:
Reducing bypass-based network-on-chip latency using priority mechanism. 1-8 - Govinda Rao Locharla
Variable length mixed radix MDC FFT/IFFT processor for MIMO-OFDM application. 9-19 - Hao Zhang
High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA. 20-29 - Sarzamin Khan
Comparative analysis of network-on-chip simulation tools. 30-38
Volume 12, Number 2, March 2018
- Ahmad A. Hiasat
Sign detector for the extended four-moduli set { 2n - 1 , 2n + 1 , 22n + 1 , 2n + k }. 39-43 - Chien-Hui Liao
Online task scheduler in 3D-MCPs with TADVA. 44-52 - Hoda Ahmadinejad, Omid Fatemi:
Moving towards grey-box predictive models at micro-architecture level by investigating inherent program characteristics. 53-61 - Shahzad Asif, Oskar Andersson
65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography. 62-67
Volume 12, Number 3, May 2018
- Simi Zerine Sleeba, John Jose
Energy-efficient fault tolerant technique for deflection routers in two-dimensional mesh Network-on-Chips. 69-79 - Irith Pomeranz:
On-chip generation of primary input sequences for multicycle functional broadside tests. 80-86 - Yang Zhang, Zuocheng Xing, Chuan Tang, Cang Liu:
Locality-protected cache allocation scheme with low overhead on GPUs. 87-94 - Nehal N. Shah, Upena D. Dalal:
Register array-based sum of absolute difference processor with parallel memory system for fast motion estimation. 95-104 - Hao Xiao, Xiang Yin, Ning Wu, Xin Chen
VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors. 105-110 - Yanyun Tao, Yuzhen Zhang, Qinyu Wang, Jian Cao:
MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis. 111-120
Volume 12, Number 4, July 2018
- Guest Editorial: Bio-inspired Hardware and Evolvable Systems. 121
- Steven D. Pyle, Kerem Yunus Çamsari
Hybrid spin-CMOS stochastic spiking neuron for high-speed emulation of In vivo neuron dynamics. 122-129 - George Martin, Jim Harkin, L. J. McDaid, John J. Wade
On-chip communication for neuro-glia networks. 130-138 - Vojtech Mrazek
Role of circuit representation in evolutionary design of energy-efficient approximate circuits. 139-149 - Javier Olivito, Felipe Serrano
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array. 150-157 - Changqing Xu
Unified multi-objective mapping for network-on-chip using genetic-based hyper-heuristic algorithms. 158-166 - Chandan Bandyopadhyay, Shalini Parekh, Hafizur Rahaman
Improved circuit synthesis approach for exclusive-sum-of-product-based reversible circuits. 167-175 - Harpreet Vohra
Test data compression using hierarchical block merging technique. 176-185
Volume 12, Number 5, September 2018
- Che Wun Chiou, Cheng-Min Lee, Yuh-Sien Sun, Chiou-Yng Lee, Jim-Min Lin:
High-throughput Dickson basis multiplier with a trinomial for lightweight cryptosystems. 187-191 - Rourab Paul
Hardware variant NSP with security-aware automated preferential algorithm. 192-205 - Sunil Dutt, Sukumar Nandi
Accuracy enhancement of equal segment based approximate adders. 206-215 - Rourab Paul
Partitioned security processor architecture on FPGA platform. 216-226 - Xiang Wang, Lin Li, Weike Wang
Online learning based on a novel cost function for system power management. 227-232 - Irith Pomeranz:
Static test compaction procedure for large pools of multicycle functional broadside tests. 233-240 - Youngchan Kim, Taewhan Kim:
Synthesis and exploration of clock spines. 241-248
Volume 12, Number 6, November 2018
- Guest Editorial: Hardware-Assisted Techniques for Security and Protection of Consumer Electronics. 249-250
- Seyed Mohammad Sebt, Ahmad Patooghy
Circuit enclaves susceptible to hardware Trojans insertion at gate-level designs. 251-257 - He Li, Qiang Liu, Fuqiang Chen:
Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits. 258-267 - Deepak Kachave, Anirban Sengupta, Shubha Neema, Panugothu Sri Harsha:
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation. 268-278 - Saman Kaedi, Mohammad-Ali Doostari, Mohammad Bagher Ghaznavi Ghoushchi
Low-complexity and differential power analysis (DPA)-resistant two-folded power-aware Rivest-Shamir-Adleman (RSA) security schema implementation for IoT-connected devices. 279-288 - Paul A. Wortman
P2M-based security model: security enhancement using combined PUF and PRNG models for authenticating consumer electronic devices. 289-296 - Daniel Brown, Ava Hedayatipour, Md. Badruddoja Majumder, Garrett S. Rose
Practical realisation of a return map immune Lorenz-based chaotic stream cipher in circuitry. 297-305
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-22 18:48 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: