default search action
7th FCCM 1999: Napa, CA, USA
- 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA. IEEE Computer Society 1999, ISBN 0-7695-0375-6
Tools 1
- João M. P. Cardoso, Horácio C. Neto:
Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System. 2-11 - Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting:
A CAD Suite for High-Performance FPGA Design. 12-24 - Satnam Singh, Carl Johan Lillieroth:
Formal Verification of Reconfigurable Cores. 25-
Network Applications
- Toshiaki Miyazaki, Takahiro Murooka, Masaru Katayama, Atsushi Takahara:
Transmutable Telecom System and Its Application. 34-43 - Jason R. Hess, David C. Lee, Scott J. Harper, Mark T. Jones, Peter M. Athanas:
Implementation and Evaluation of a Prototype Reconfigurable Router. 44-
Compilation
- Markus Weinhardt, Wayne Luk:
Pipeline Vectorization for Reconfigurable Systems. 52-62 - Maya B. Gokhale, Janice M. Stone:
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks. 63-69 - Jonathan Babb, Martin C. Rinard, Csaba Andras Moritz, Walter Lee, Matthew I. Frank, Rajeev Barua, Saman P. Amarasinghe:
Parallelizing Applications into Silicon. 70-
Architectures
- Michael R. Piacentino, Gooitzen S. van der Wal, Michael W. Hansen:
Reconfigurable Elements for a Video Pipeline Processor. 82-91 - Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge:
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. 92-
Tools 2
- Srihari Cadambi, Seth Copen Goldstein:
CPR: A Configuration Profiling Tool. 104-113 - Nicholas McKay, Satnam Singh:
Debugging Techniques for Dynamically Reconfigurable Hardware. 114-122 - Milan Vasilko, David Cabanis:
Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems. 123-
Graphics Applications
- Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung:
Reconfigurable Computing for Augmented Reality. 136-145 - Laurent Moll, Mark Shand, Alan Heirich:
Sepia: Scalable 3D Compositing Using PCI Pamette. 146-
Applications
- Zhen Luo, Margaret Martonosi, Pranav Ashar:
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking. 158-167 - José Carlos Alves, João Canas Ferreira
, C. Albuquerque, José Fernando Oliveira
FAFNER-Accelerating Nesting Problems with FPGAs. 168-
DSP Applications
- Tyler J. Moeller, David R. Martinez:
Field Programmable Gate Array Based Radar Front-End Digital Signal Processing. 178-187 - Dan Benyamin, John D. Villasenor, Wayne Luk:
Optimizing FPGA-Based Vector Product Designs. 188-
Run Time Systems
- Ronald Laufer, R. Reed Taylor, Herman Schmit:
PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing. 200-208 - Andrew A. Chien, Jay H. Byun:
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor. 209-221 - Mark Jones, Luke Scharf, Jonathan Scott, Chris Twaddle, Matthew Yaconis, Kuan Yao, Peter Athanas, Brian Schott:
Implementing an API for Distributed Adaptive Computing Systems. 222-
Arithmetic
- Gerardo Orlando, Christof Paar:
A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms. 232-239 - Monk-Ping Leong, M. Y. Yeung, C. K. Yeung, Chi-Wing Fu, Pheng-Ann Heng, Philip Heng Wai Leong:
Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping. 240-248 - Kiran Bondalapati, Viktor K. Prasanna:
Dynamic Precision Management for Loop Computations on Reconfigurable Architectures. 249-
Poster Session 1
- Jean-Paul Heron, Roger F. Woods:
Accelerating Run-Time Reconfiguration on FCCMs. 260-261 - Richard H. Turner, Roger F. Woods, Sakir Sezer, Jean-Paul Heron:
A Virtual Hardware Handler for RTR Systems. 262-263 - Eric K. Pauer, Paul D. Fiore, John M. Smith:
Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results. 264-265 - Valery Sklyarov, José A. Fonseca, Ricardo Sal Monteiro, Arnaldo S. R. Oliveira, Andreia Melo, Nuno Lau, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari:
Development System for FPGA-Based Digital Circuits. 266-267 - Cynthia Cousineau, François Laperle, Yvon Savaria:
Design of a JTAG Based Run Time Reconfigurable System. 268-269 - Brian Schott, Chen Chen, Steve Crago, Joseph Czarnaski, Matthew French, Ivan Hom, Tam Tho, Terri Valenti:
Architectures for System-Level Applications of Adaptive Computing. 270-27 - Vinoo Srinivasan, Ranga Vemuri:
Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures. 272- - Andreas Koch:
Enabling Automatic Module Generation for FCCM Compilers. 274-
Poster Session 2
- Michael Baxter:
ICARUS: A Dynamically Reconfigurable Computer Architecture. 278- - Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone:
SONIC - A Plug-In Architecture for Video Processing. 280-281 - Christof Teuscher, Jacques-Olivier Haenni, Héctor Fabio Restrepo, Eduardo Sanchez, Francisco J. Gómez:
A Reconfigurable Platform for Academic Purposes. 282-283 - James Hwang, Cameron Patterson, Sujoy Mitra:
VHDL Placement Directives for Parametric IP Blocks. 284-285 - Scott Hauck, William D. Wilson:
Runlength Compression Techniques for FPGA Configurations. 286-
Poster Session 3
- Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko:
Accelerating an IR Automatic Target Recognition Application with FPGAs. 290-291 - Benjamin A. Levine, Senthil Natarajan, Chandra Tan, Danny F. Newport, Donald W. Bouldin:
Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-Based Reconfigurable Hardware. 292-293 - Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi:
Hybrid Data/Configuration Caching for Striped FPGAs. 294-295 - Huesung Kim, Arun K. Somani, Akhilesh Tyagi:
On Reconfiguring Cache for Computing. 296-297 - Ronald D. Williams, Brian D. Kuebert:
Reconfigurable Pipelines in VLIW Execution Units. 298-299 - Kiarash Barzagan, Majid Sarrafzadeh:
Fast Online Placement for Reconfigurable Computing. 300-
Poster Session 4
- Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman:
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor. 304-305 - Miron Abramovici, José T. de Sousa:
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. 306-307 - Pak K. Chan, Mark J. Boyd, Sezer Gören, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, Katsuharu Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu:
Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. 308-309 - Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor:
FPGA-Based Structures for On-Line FFT and DCT. 310-311 - Luiz Maltar, Felipe M. G. França
An FPGA-Based Fan Beam Image Reconstruction Module. 312-313 - Donald MacVicar, Satnam Singh, Robert Slous:
Bézier Curve Rendering on Virtex(tm). 314-
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-17 20:47 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: