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Cameron Patterson
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2020 – today
- 2024
- [c25]Behnaz Rezvani, Cameron Patterson:
A Monitoring Methodology and Framework to Partition Embedded Systems Requirements. ENASE 2024: 563-570 - 2023
- [c24]Behnaz Rezvani, Cameron Patterson:
Differentiated Monitor Generation for Real-Time Systems. ICSOFT 2023: 353-360
2010 – 2019
- 2019
- [c23]Howard McDonald, Joy Cantalupo, Mike DiFrancisco, Anthony Rennier, Darcy Swain-Walsh, Jeffrey T. Correia, Venkatesh Ramaswamy, Cameron Patterson:
AWS-3 Interference Mitigation: Improving Spectrum Sharing with LTE & 5G Uplink Spectrum Control. MILCOM 2019: 102-107 - [c22]Darcy Swain-Walsh, Jeffrey T. Correia, Venkatesh Ramaswamy, Cameron Patterson, Howard McDonald, Josephine Cantalupo, Anthony Rennier, Mike DiFrancisco:
High-Fidelity LTE Waveform Modeling for Commercial-DoD Spectrum Sharing: Characteristics and Methods. MILCOM 2019: 125-130 - 2018
- [c21]Howard McDonald, D. J. Shyy, Matt Steele, Cameron Patterson:
LTE Uplink Interference Mitigation Features. MILCOM 2018: 505-511 - 2014
- [c20]Samantha V. Adams, Alexander D. Rast, Cameron Patterson, Francesco Galluppi, Kevin Brohan, José Antonio Pérez-Carrasco, Thomas Wennekers, Steve B. Furber, Angelo Cangelosi:
Towards Real-World Neurorobotics: Integrated Neuromorphic Visual Attention. ICONIP (3) 2014: 563-570 - [c19]Evangelos Stromatias, Cameron Patterson, Steve B. Furber:
Optimising the overall power usage on the SpiNNaker neuromimetic platform. IJCNN 2014: 4280-4287 - 2013
- [j7]Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Francesco Galluppi, Cameron Patterson, David R. Lester, Andrew D. Brown, Steve B. Furber:
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. IEEE J. Solid State Circuits 48(8): 1943-1953 (2013) - [j6]Javier Navaridas, Steve B. Furber, Jim D. Garside, Xin Jin, Mukaram M. Khan, David R. Lester, Mikel Luján, José Miguel-Alonso, Eustace Painkras, Cameron Patterson, Luis A. Plana, Alexander D. Rast, Dominic Richards, Yebin Shi, Steve Temple, Jian Wu, Shufan Yang:
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. Parallel Comput. 39(11): 693-708 (2013) - [c18]Aydin Aysu, Cameron Patterson, Patrick Schaumont:
Low-cost and area-efficient FPGA implementations of lattice-based cryptography. HOST 2013: 81-86 - [c17]Qian Liu, Cameron Patterson, Steve B. Furber, Zhangqin Huang, Yibin Hou, Huibing Zhang:
Modeling populations of spiking neurons for fine timing sound localization. IJCNN 2013: 1-8 - [c16]Evangelos Stromatias, Francesco Galluppi, Cameron Patterson, Steve B. Furber:
Power analysis of large-scale, real-time neural networks on SpiNNaker. IJCNN 2013: 1-8 - 2012
- [j5]Alexander D. Rast, Javier Navaridas, Xin Jin, Francesco Galluppi, Luis A. Plana, José Miguel-Alonso, Cameron Patterson, Mikel Luján, Steve B. Furber:
Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System. Int. J. Parallel Program. 40(6): 553-582 (2012) - [j4]Cameron Patterson, Jim D. Garside, Eustace Painkras, Steve Temple, Luis A. Plana, Javier Navaridas, Thomas Sharp, Steve B. Furber:
Scalable communications for a million-core neural processing architecture. J. Parallel Distributed Comput. 72(11): 1507-1520 (2012) - [c15]Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve B. Furber:
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. CICC 2012: 1-4 - [c14]Cameron Patterson, Thomas Preston, Francesco Galluppi, Steve B. Furber:
Managing a Massively-Parallel Resource-Constrained Computing Architecture. DSD 2012: 723-726 - [c13]Cameron Patterson, Francesco Galluppi, Alexander D. Rast, Steve B. Furber:
Visualising large-scale neural network models in real-time. IJCNN 2012: 1-8 - 2011
- [j3]Alexander D. Rast, Francesco Galluppi, Sergio Davies, Luis A. Plana, Cameron Patterson, Thomas Sharp, David R. Lester, Steve B. Furber:
Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware. Neural Networks 24(9): 961-978 (2011) - [j2]Mukaram M. Khan, Alexander D. Rast, Javier Navaridas, X. Jin, Luis A. Plana, Mikel Luján, Steve Temple, Cameron Patterson, Dominic Richards, John V. Woods, José Miguel-Alonso, Stephen B. Furber:
Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric. Parallel Comput. 37(8): 392-409 (2011) - [c12]Thomas Sharp, Cameron Patterson, Steve B. Furber:
Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware. IJCNN 2011: 1099-1105 - 2010
- [j1]Sergio Davies, Cameron Patterson, Francesco Galluppi, Alexander D. Rast, David R. Lester, Steve B. Furber:
Interfacing Real-Time Spiking I/O with the SpiNNaker Neuromimetic Architecture. Aust. J. Intell. Inf. Process. Syst. 11(1) (2010) - [c11]Alexander D. Rast, Xin Jin, Francesco Galluppi, Luis A. Plana, Cameron Patterson, Stephen B. Furber:
Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system. Conf. Computing Frontiers 2010: 21-30 - [c10]Xin Jin, Francesco Galluppi, Cameron Patterson, Alexander D. Rast, Sergio Davies, Steve Temple, Steve B. Furber:
Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system. IJCNN 2010: 1-8
2000 – 2009
- 2003
- [c9]Cameron Patterson:
A Dynamic Module Server for Embedded Platform FPGAs. Engineering of Reconfigurable Systems and Algorithms 2003: 31-40 - 2001
- [c8]Cameron Patterson, Steven A. Guccione:
JBits™ Design Abstractions. FCCM 2001: 251-252 - [c7]Scott McMillan, Cameron Patterson:
JBitsTM Implementations of the Advanced Encryption Standard (Rijndael). FPL 2001: 162-171 - [c6]Tim Price, Cameron Patterson:
Reconfigurable Breakpoints for Co-debug. FPL 2001: 473-482 - 2000
- [c5]Cameron Patterson:
A Dynamic FPGA Implementation of the Serpent Block Cipher. CHES 2000: 141-155 - [c4]Cameron Patterson:
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm). FCCM 2000: 113-121
1990 – 1999
- 1999
- [c3]James Hwang, Cameron Patterson, Sujoy Mitra:
VHDL Placement Directives for Parametric IP Blocks. FCCM 1999: 284-285 - [c2]James Hwang, Cameron Patterson, Sujoy Mitra:
Hierarchical Placement Directives for Parametric IP Blocks. FPGA 1999: 250 - 1998
- [c1]James Hwang, Cameron Patterson, S. Mohan, Eric Dellinger, Sujoy Mitra, Ralph Wittig:
Generating Layouts for Self-implementing Modules. FPL 1998: 525-529
Coauthor Index
aka: Stephen B. Furber
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