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"Instruction buffering to reduce power in processors for signal processing."

Raminder Singh Bajwa et al. (1997)

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DOI: 10.1109/92.645068

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - journals/tvlsi/BajwaHKGNSSS97
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  - https://dblp.org/rec/journals/tvlsi/BajwaHKGNSSS97
Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki:
Instruction buffering to reduce power in processors for signal processing. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 417-424 (1997)

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