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Katsuro Sasaki
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1990 – 1999
- 1997
- [j7]Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki:
Instruction buffering to reduce power in processors for signal processing. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 417-424 (1997) - 1996
- [c1]Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki:
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. ISLPED 1996: 353-358 - 1995
- [j6]Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome:
A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. IEEE J. Solid State Circuits 30(3): 251-257 (1995) - [j5]Hirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki:
Half-swing clocking scheme for 75% power saving in clocking circuitry. IEEE J. Solid State Circuits 30(4): 432-435 (1995) - [j4]Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome:
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. IEEE J. Solid State Circuits 30(4): 487-490 (1995) - [j3]Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome:
Trends in low-power RAM circuit technologies. Proc. IEEE 83(4): 524-543 (1995) - 1994
- [j2]Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki:
A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. IEEE J. Solid State Circuits 29(4): 411-418 (1994)
1980 – 1989
- 1989
- [j1]Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo:
A 9-ns 1-Mbit CMOS SRAM. IEEE J. Solid State Circuits 24(5): 1219-1225 (1989)
Coauthor Index
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