default search action

combined dblp search
author search
venue search
publication search

ask others

"A high-speed VLSI design and ASIC implementation for constructing ..."

Natarajan Sudha, K. Sridharan (2004)

> Home

Details and statistics

DOI: 10.1109/TRA.2004.824638

access: closed

type: Journal Article

metadata version: 2020-05-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/trob/SudhaS04
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/trob/SudhaS04
Natarajan Sudha, K. Sridharan:
A high-speed VLSI design and ASIC implementation for constructing Euclidean distance-based discrete Voronoi diagram. IEEE Trans. Robotics Autom. 20(2): 352-358 (2004)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.