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"A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High ..."

Simone Zezza, Saeid Nooshabadi, Guido Masera (2013)

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DOI: 10.1109/TCSI.2012.2209292

access: closed

type: Journal Article

metadata version: 2020-05-22

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  - https://dblp.org/rec/journals/tcas/ZezzaNM13
Simone Zezza, Saeid Nooshabadi, Guido Masera:
A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 951-964 (2013)

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