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"A 65nm CMOS Ramp Generator Design and its Application Towards a BIST ..."

Guillaume Renaud et al. (2016)

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DOI: 10.1007/S10836-016-5599-8

access: closed

type: Journal Article

metadata version: 2023-06-28

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Guillaume Renaud, Manuel J. Barragán, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet:
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electron. Test. 32(4): 407-421 (2016)

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