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"A 5.5 GHz low-power PLL using 0.18-µm CMOS technology."

Jeng-Han Tsai, Shao-Wei Huang, Jian-Ping Chou (2014)

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DOI: 10.1109/RWS.2014.6830071

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Jeng-Han Tsai, Shao-Wei Huang, Jian-Ping Chou:
A 5.5 GHz low-power PLL using 0.18-µm CMOS technology. RWS 2014: 205-207

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