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"A scalable architecture for VLSI test."

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Ed Chang et al. (1998)

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DOI: 10.1109/TEST.1998.743192

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Ed Chang, David Cheung, Robert E. Huston, Jim Seaton, Gary Smith:
A scalable architecture for VLSI test. ITC 1998: 500-506

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last updated on 2023-03-23 23:58 CET by the dblp team

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