default search action

combined dblp search
author search
venue search
publication search

ask others

"The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays."

M. S. Hrishikesh et al. (2002)

> Home

Details and statistics

DOI: 10.1109/ISCA.2002.1003558

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/isca/HrishikeshBKSJF02
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isca/HrishikeshBKSJF02
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas:
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. ISCA 2002: 14-24

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.