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"On Transistor Level Gate Sizing for Increased Robustness to Transient Faults."

José Manuel Cazeaux et al. (2005)

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DOI: 10.1109/IOLTS.2005.49

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/iolts/CazeauxROMC05
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  persistent URL:
  - https://dblp.org/rec/conf/iolts/CazeauxROMC05
José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee:
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. IOLTS 2005: 23-28

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