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"Memory System Design for Ultra Low Power, Computationally Error Resilient ..."

Sriseshan Srikanth et al. (2018)

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DOI: 10.1109/HPCA.2018.00065

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

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  - conf/hpca/SrikanthRHDCDCF18
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  - https://dblp.org/rec/conf/hpca/SrikanthRHDCDCF18
Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank:
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA 2018: 696-709

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