default search action

combined dblp search
author search
venue search
publication search

ask others

"A wave-pipelined router architecture using ternary associative memory."

José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan (2000)

> Home

Details and statistics

DOI: 10.1145/330855.330971

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/Delgado-FriasNB00
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/Delgado-FriasNB00
José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan:
A wave-pipelined router architecture using ternary associative memory. ACM Great Lakes Symposium on VLSI 2000: 67-70

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.