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"SSR: Spatial Sequential Hybrid Architecture for Latency Throughput ..."

Jinming Zhuang et al. (2024)

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DOI: 10.1145/3626202.3637569

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-15

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  dblp key:
  - conf/fpga/ZhuangYJHJH0024
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  - https://dblp.org/rec/conf/fpga/ZhuangYJHJH0024
Jinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi, Peipei Zhou:
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. FPGA 2024: 55-66

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