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"A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and ..."

Koh Johguchi et al. (2007)

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DOI: 10.1109/ESSCIRC.2007.4430308

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-18

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  - conf/esscirc/JohguchiMIMK07
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  - https://dblp.org/rec/conf/esscirc/JohguchiMIMK07
Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide:
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. ESSCIRC 2007: 320-323

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