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"A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point ..."

Timothy Anderson et al. (2011)

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DOI: 10.1109/ARITH.2011.20

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - conf/arith/AndersonBMNRLBSDYM10
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  persistent URL:
  - https://dblp.org/rec/conf/arith/AndersonBMNRLBSDYM10
Timothy Anderson, Duc Bui, Shriram Moharil, Soujanya Narnur, Mujibur Rahman, Anthony Lell, Eric Biscondi, Ashish Shrivastava, Peter Dent, Mingjian Yan, Hasan Mahmood:
A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS. IEEE Symposium on Computer Arithmetic 2011: 82-86

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