default search action

combined dblp search
author search
venue search
publication search

ask others

"Cimple: instruction and memory level parallelism: a DSL for uncovering ILP ..."

Vladimir Kiriansky et al. (2018)

> Home

Details and statistics

DOI: 10.1145/3243176.3243185

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/IEEEpact/KirianskyXRA18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/IEEEpact/KirianskyXRA18
Vladimir Kiriansky, Haoran Xu, Martin C. Rinard, Saman P. Amarasinghe:
Cimple: instruction and memory level parallelism: a DSL for uncovering ILP and MLP. PACT 2018: 30:1-30:16

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.