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"A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC ..."

Yohan Frans et al. (2016)

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DOI: 10.1109/VLSIC.2016.7573474

access: closed

type: Conference or Workshop Paper

metadata version: 2021-09-30

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  - conf/vlsic/FransEHIKPSUZAB16
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  - https://dblp.org/rec/conf/vlsic/FransEHIKPSUZAB16
Yohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang:
A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. VLSI Circuits 2016: 1-2

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