default search action

combined dblp search
author search
venue search
publication search

ask others

"Early planning for RT-level delay insertion during clock skew-aware ..."

Keisuke Inoue, Mineo Kaneko (2011)

> Home

Details and statistics

DOI: 10.1109/VLSISOC.2011.6081638

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsi/InoueK11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/InoueK11
Keisuke Inoue, Mineo Kaneko:
Early planning for RT-level delay insertion during clock skew-aware register binding. VLSI-SoC 2011: 154-159

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.